K7D323674A
K7D321874A
1Mx36 & 2Mx18 SRAM
32Mb A-die DDR SRAM Specification
153FCBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
Document Title
32M DDR SYNCHRONOUS SRAM
1Mx36 & 2Mx18 SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.1
History
Initial document.
Remove /G operation thru the Spec.
- Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURA-
TION, TRUTH TABLE and TIMING WAVEFORMs
Add 300MHz Speed bin.
- Add Part ID at ORDERING INFORMATION & I
DD30
at DC CHARACTERIS-
TICS
Change I
LI
and I
Lo
at DC CHARCATERISTICS
- I
LI
: MIN -1 -> -3, MAX 1 -> 3, I
Lo
: MIN -1 -> -5, MAX 1 -> 5
Change the comment of Programmable Impedance Output Driver.
Change RECOMMENDED DC OPERATING CONDITIONS.
- V
REF
: Min 0.68 -> 0.65, Max 1.0 -> 0.85
Change PIN CAPACITANCE : C
IN
: 3 -> 3.1
Change AC TEST CONDITIONS : T
R
/R
F
: 0.4/0.4 -> 0.5/0.5
Change AC TIMING CHARACTERISTICS
- t
CHCL
: t
KHKL
-0.1 -> t
KHKL
-0.2 , t
CLCH
: t
KLKH
-0.1 -> t
KLKH
-0.2
- t
CXCV
: 2.10 -> 2.30
Rev 0.2
Change VDDQ RANGE
- In FEATURES : 1.5V V
DDQ
-> 1.5~.1.8V V
DDQ
- In RECOMENDED DC OPERATING CONDITIONS : Max V
DDQ
: 1.6 -> 1.9
Change TRUTH TABLE : Remove Clock Stop
Change DC CHARACTERISTICS
- x36 I
DD
:
I
DD50
: 950 -> 1050, I
DD45
: 850 -> 950, I
DD40
: 800 -> 860, I
DD30
: 750 -> 760
- x18 I
DD
:
I
DD50
: 850 -> 1000, I
DD45
: 800 -> 900, I
DD40
: 750 -> 810, I
DD30
: 700 -> 710
- I
SB1
: 150 -> 200
Change PIN CAPACITANCE : C
IN
: 3.1 -> 3.2, C
OUT
: 4 -> 4.2
Change AC TIMING CHARACTERISTICS
- MIN t
KHKL,
t
KHKL
: -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4
- MIN t
AVKH,
t
BVKH,
t
KHAX,
t
KHBX
: -45 : 0.25 -> 0.27
- t
KXCV
MIN/MAX : 0.8/2.3 -> 1.0/2.5
Change PACKAGE THERMAL CHARACTERISTICS
Feb. 2003
Advance
Draft Data
Dec. 2002
Jan. 2003
Remark
Advance
Advance
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-2-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
Revision History
Rev No.
Rev 0.3
History
1Mx36 & 2Mx18 SRAM
Draft Data
May. 2003
Remark
Advance
Change DC CHARACTERISTICS
- x36 I
DD
:
I
DD50
: 1050 -> 1150 , I
DD45
: 950 -> 1050, I
DD40
: 860 -> 960, I
DD30
: 760 ->
860
- x18 I
DD
:
I
DD50
: 1000 -> 1100, I
DD45
: 900 -> 1000, I
DD40
: 810 -> 910, I
DD30
: 710 ->
810
- I
SB1
: 200 -> 300
Change 300Mhz speed bin to 333Mhz
Change PIN CONFIGURATIONS
- change DQ pin number
Change AC CHARACTERISTICS
- t
CHCL
, t
CLCH
: -/+0.2 -> -/+ 0.1
Rev 0.4
Rev 0.5
Jun. 2003
Aug. 2003
Advance
Advance
Rev 0.6
Change AC CHARACTERISTICS
- Remove : t
QTRK
, t
CXCV
- Add : t
CXCH,
t
CXCL,
t
CHQV,
t
CLQV,
t
CHQX,
t
CLQX,
t
CLQZ,
t
CHLZ
Add Power-Up/Power-Down Supply Voltage Sequencing
Change PACKAGE PIN CONFIGURATIONS
- Remove the number at DQ pins
Change Bin
- 50, 45, 40, 33 -> 40, 37, 33
Change the word in READ OPERATION
- at least one NOP -> at least two NOP
Add AC INPUT CHARACTERISTICS and AC INPUT DEFINITION.
Remove the comment for DDR3 from Spec.
Modify AC TIMING CHARACTERISTICS
- clock high/low pulse width : -40 : 1.2 -> 1.15
- remove min. value of t
CHQV
and t
CLQV
Add Pb free.
Sep. 2003
Advance
Rev 0.7
Rev 0.8
Sep. 2003
Oct. 2003
Advance
Advance
Rev 0.9
Feb. 2003
Advance
Rev 1.0
Mar. 2003
Final
Rev 1.1
Rev 1.2
Rev 1.3
Apr. 2004
Jun. 2004
Jan. 2005
Final
Final
Final
Rev 1.4
Oct. 2005
Final
-3-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
FEATURES
•
•
•
•
•
1Mx36 or 2Mx18 Organizations.
1.8~2.5V V
DD
/1.5V ~1.8V
DDQ
.
HSTL Input and Outputs.
Single Differential HSTL Clock.
Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Registered Addresses, Burst Control and Data Inputs.
1Mx36 & 2Mx18 SRAM
• Registered Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Flip Chip Ball Grid Array Package(14mmx22mm)
• No Output enable support.
GENERAL DESCRIPTION
The K7D323674A and K7D321874A are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
1,048,576 words by 36 bits for K7D323674A and 2,097,152 words by 18 bits for K7D321874A, fabricated using Samsung's
advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access
time for all SDR and DDR operations.
The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid
Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Part Number
K7D323674A-H(G)C40
K7D323674A-H(G)C37
K7D323674A-H(G)C33
K7D321874A-H(G)C40
K7D321874A-H(G)C37
K7D321874A-H(G)C33
* G : Lead free package
Organization
Maximum
Frequency
400MHz
1Mx36
375MHz
333MHz
400MHz
2Mx18
375MHz
333MHz
-4-
Rev 1.4
Oct. 2005
K7D323674A
K7D321874A
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
Address
Register
CE
20(or 21)
18(or 19)
(Burst Address)
Burst
Counter
(Burst Write
Address)
20(or 21)
18(or 19)
2:1
MUX
1Mx36 & 2Mx18 SRAM
Dec.
Data Out
K,K
Clock
Buffer
Memory Array
1Mx36
or
(2Mx18)
Data In
36(or18)x2
W/D
Array
36(or18)x2
Write Buffer
Comparator
B
1
B
3
Advance
Co
Control
SD/DD
Write
Address
Register
(2 stage)
CE
Synchronous
Select
&
R/W control
CE
R/W
LD
Internal
Clock
Generator
Data Output Strobe
Data Output Enable
State Machine
Strobe_out
36(or 18)x2
S/A Array
36(or 18)x2
2 : 1 MUX
B
2
Output
Buffer
Echo Clock
Output
Data In
Register
(2 stage)
36(or 18)
DQ
CQ,CQ
XDIN
PIN DESCRIPTION
Pin Name
K, K
SA
SA
0
, SA
1
DQ
CQ, CQ
B
1
B
2
B
3
LBO
ZQ
Pin Description
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input (SA
0
= LSB)
Synchronous Data I/O
Differential Output Echo Clocks
Load External Address
Burst R/W Enable
Single/Double Data Selection
Linear Burst Order
Output Driver Impedance Control Input
Pin Name
TCK
TMS
TDI
TDO
V
REF
V
DD
V
DDQ
V
SS
NC
Pin Description
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
-5-
Rev 1.4
Oct. 2005
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