Features
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32-Mbit DataFlash and 4-Mbit SRAM
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Single 62-ball (8 mm x 12 mm x 1.2 mm) CBGA Package
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2.7V to 3.3V Operating Voltage
DataFlash
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•
•
•
•
•
•
•
•
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Single 2.7V to 3.3V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (528 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 528-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
Industrial Temperature Range
32-megabit
DataFlash
®
+ 4-megabit
SRAM
Stack Memory
AT45BR3214B
SRAM
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4-megabit (256K x 16)
2.7V to 3.3V V
CC
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
Rev. 3356B–DFLASH–10/04
1
Pin Configuration
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
VCC
GND
A0 - A17
I/O0 - I/O15
SLB
SUB
SVCC
SGND
SCS1
SCS2
SWE
SOE
NC
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Write Protect
Reset
READY BUSY
Flash Power Supply
Flash Ground
SRAM Address Input
SRAM Data Inputs/Outputs
SRAM Lower Byte
SRAM Upper Byte
SRAM Power
SRAM Ground
SRAM Chip Select 1
SRAM Chip Select 2
SRAM Write Enable
SRAM Output Enable
No Connect
AT45BR3214B
(Top View)
1
A
NC
SI
A16
A11
A8
A15
A10
A14
A9
A13
A12
GND
NC
I/O7
I/O5
NC
2
3
4
5
6
7
8
9
10
B
I/O15 SWE I/O14
I/O13
I/O6
I/O4
C
WP
RDY/BUSY
D
SGND RESET
I/O12 SCS2 SVCC VCC
NC
SOE
A7
A4
A6
A0
I/O11
I/O9
A3
CS
I/O10
I/O8
A2
GND
I/O2
I/O0
A1
SCK
I/O3
I/O1
SCS1
NC
NC
E
NC
NC
SUB
A17
A5
F
SLB
G
SO
H
NC
NC
2
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Block Diagram
SI WP
ADDRESS
SOE SWE
RESET
CS
SCK
RDY/BUSY
32-Mbit
DataFlash
4-Mbit
SRAM
SCS1
SCS2
SO
DATA (I/O0 - I/O15)
Description
The AT45BR3214B combines a 32-megabit DataFlash (32M x 1) and a 4-megabit
SRAM (organized as 256K x 16) in a stacked 62-ball CBGA package. The stacked mod-
ule operates at 2.7V to 3.3V in the industrial temperature range.
Absolute Maximum Ratings
Temperature under Bias .................................. -40°C to +85°C
Storage Temperature ..................................... -55°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC and AC Operating Range
AT45BR3214B
Operating Temperature (Case)
V
CC
Power Supply
Industrial
-40°C - 85°C
2.7V to 3.3V
3
3356B–DFLASH–10/04
32-Mbit DataFlash
Description
The 32-Mbit DataFlash is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-
tion to the main memory, the 32-Mbit DataFlash also contains two SRAM data buffers of
528 bytes each. The buffers allow receiving of data while a page in the main memory is
being reprogrammed, as well as reading or writing a continuous data-stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step
Read-Modify-Write operation. Unlike conventional Flash memories that are accessed
randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI
serial interface to sequentially access its data. DataFlash supports SPI mode 0 and
mode 3. The simple serial interface facilitates hardware layout, increases system reli-
ability, minimizes switching noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and industrial applications where high
density, low pin count, low voltage, and low power are essential. The device operates at
clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the 32-Mbit DataFlash does not
require high input voltages for programming. The device operates from a single power
supply, 2.7V to 3.3V, for both the program and read operations. The 32-Mbit DataFlash
is enabled through the chip select pin (CS) and accessed via a three-wire interface con-
sisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming. When the device is shipped from Atmel, the most significant page of the
memory array may not be erased. In other words, the contents of the last page may not
be filled with FFH.
DataFlash
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 (528 BYTES)
BUFFER 2 (528 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the 32-Mbit DataFlash is divided into
three levels of granularity comprising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
4
AT45BR3214B
3356B–DFLASH–10/04
AT45BR3214B
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 4224 bytes (4K + 128)
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0
BLOCK 1
PAGE ARCHITECTURE
8 Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR 1
SECTOR 1 = 266,112 bytes (252K + 8064)
BLOCK 2
PAGE 6
PAGE 7
PAGE 8
SECTOR 2 = 270,336 bytes (256K + 8K)
BLOCK 62
BLOCK 63
SECTOR 2
BLOCK 65
BLOCK 1
BLOCK 64
PAGE 9
PAGE 14
PAGE 15
BLOCK 126
BLOCK 127
SECTOR 15 = 270,336 bytes (256K + 8K)
BLOCK 128
BLOCK 129
PAGE 16
PAGE 17
PAGE 18
PAGE 8189
SECTOR 16 = 270,336 bytes (256K + 8K)
BLOCK 1022
BLOCK 1023
PAGE 8190
PAGE 8191
Block = 4224 bytes
(4K + 128)
Page = 528 bytes
(512 + 16)
Device Operation
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0
where PA12 - PA0 denotes the 13 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 11 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ:
By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
5
3356B–DFLASH–10/04
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