Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 7
Chapter 2. Functional Description ........................................................................................................ 9
General Description of the CORDIC Algorithm ..................................................................................................... 9
Block Diagram..................................................................................................................................................... 11
Data Path ................................................................................................................................................... 11
CORDIC Functions .................................................................................................................................... 12
Interface Diagram................................................................................................................................................ 14
Configuring the CORDIC IP Core ....................................................................................................................... 15
Basic Options ............................................................................................................................................. 15
Advanced Options...................................................................................................................................... 16
Timing Specifications .......................................................................................................................................... 18
Chapter 3. Parameter Settings ............................................................................................................ 20
Basic Options Tab............................................................................................................................................... 20
Mode .......................................................................................................................................................... 21
Architecture ................................................................................................................................................ 21
Iterations .................................................................................................................................................... 21
Compensation ............................................................................................................................................ 21
Pre-Rotation ............................................................................................................................................... 21
Advanced Options Tab........................................................................................................................................ 21
Data Width ................................................................................................................................................. 21
Rounding.................................................................................................................................................... 21
Optional Ports ............................................................................................................................................ 21
Synthesis Options ...................................................................................................................................... 22
Chapter 4. IP Core Generation............................................................................................................. 23
Licensing the IP Core.......................................................................................................................................... 23
Getting Started .................................................................................................................................................... 23
IPexpress-Created Files and Top Level Directory Structure............................................................................... 25
Instantiating the Core ......................................................................................................................................... 27
Running Functional Simulation .......................................................................................................................... 27
Synthesizing and Implementing the Core in a Top-Level Design ...................................................................... 27
Hardware Evaluation........................................................................................................................................... 28
Enabling Hardware Evaluation in Diamond................................................................................................ 28
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 28
Updating/Regenerating the IP Core .................................................................................................................... 28
Regenerating an IP Core in Diamond ........................................................................................................ 29
Regenerating an IP Core in ispLEVER ...................................................................................................... 29
Chapter 5. Core Verification ................................................................................................................ 31
Chapter 6. Support Resources ............................................................................................................ 32
Lattice Technical Support.................................................................................................................................... 32
Online Forums............................................................................................................................................ 32
Telephone Support Hotline ........................................................................................................................ 32
E-mail Support ........................................................................................................................................... 32
Local Support ............................................................................................................................................. 32
Internet ....................................................................................................................................................... 32
References.......................................................................................................................................................... 32
LatticeEC/ECP ........................................................................................................................................... 32
LatticeECP2M ............................................................................................................................................ 33
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CORDIC IP Core User’s Guide
Table of Contents
LatticeECP3 ............................................................................................................................................... 33
LatticeSCM................................................................................................................................................. 33
LatticeXP.................................................................................................................................................... 33
LatticeXP2.................................................................................................................................................. 33
Revision History .................................................................................................................................................. 33
............................................................................................................................................................................ 33
Appendix A. Resource Utilization ....................................................................................................... 34
LatticeEC Devices............................................................................................................................................... 34
Ordering Part Number................................................................................................................................ 34
LatticeECP Devices ............................................................................................................................................ 35
Ordering Part Number................................................................................................................................ 35
LatticeECP2 Devices .......................................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
LatticeECP2M Devices ....................................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
LatticeECP3 Devices .......................................................................................................................................... 36
Ordering Part Number................................................................................................................................ 36
LatticeSC and LatticeSCM Devices .................................................................................................................... 36
Ordering Part Number................................................................................................................................ 36
LatticeXP Devices ............................................................................................................................................... 36
Ordering Part Number................................................................................................................................ 36
LatticeXP2 Devices ............................................................................................................................................. 37
Ordering Part Number................................................................................................................................ 37
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CORDIC IP Core User’s Guide
Chapter 1:
Introduction
This user’s guide provides a description of Lattice’s Coordinate Rotation Digital Computer (CORDIC) IP core. The
CORDIC IP core is configurable and supports several functions, including rotation, translation, sin and cos, and
arctan. Two architecture configurations are supported for the arithmetic unit: parallel, in which the output data is
calculated in a single clock cycle, and word-serial, in which the output data is calculated over multiple clock cycles.
The input and output data widths and computation iterative numbers are configurable over a wide range of values.
The IP core uses full precision arithmetic internally while supporting variable output precision and several choices
of rounding algorithms.
Quick Facts
Table 1-1
through
Table 1-7
give quick facts about the CORDIC IP core for LatticeECP™, LattceECP2™,
LatticeECP2M™, LatticeECP3™, LatticeSC/M™, LatticeXP™, and LatticeXP2™ devices, respectively.
Table 1-1. CORDIC IP Core for LatticeECP Devices Quick Facts
CORDIC IP Configuration
Rotate
Parallel
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Resource
Utilization
Data Path Width
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
LFECP6E-
3T114
LFECP20E-
5F484C
16
1300
0
1300
Translate
Parallel
LFECP6E-
3T114
LFECP20E-
5F484C
16
1200
0
1200
Rotate
Serial
LFECP6E-
3T114
LFECP20E-
5F484C
16
600
0
300
Translate
Serial
LFECP6E-
3T114
LFECP20E-
5F484C
16
700
0
400
LatticeECP
Lattice Diamond™ 1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify™ Pro for Lattice D-2009.12L-1
Aldec
®
Active-HDL™ 8.2 Lattice Edition
Mentor Graphics
®
ModelSim™ SE 6.3F
IPUG81_1.3, August 2012
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CORDIC IP Core User’s Guide
Analog electronics
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