Data Sheet
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
Two Selectable Inputs, 8 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK948
FUNCTIONAL BLOCK DIAGRAM
LVPECL
ADCLK948
Q0
Q0
Q1
Q1
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
Q2
Q2
Q3
REFERENCE
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
IN_SEL
Q7
REFERENCE
V
REF
0
V
T
0
CLK0
CLK0
GENERAL DESCRIPTION
The ADCLK948 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
V
REF
x pin is available for biasing ac-coupled inputs.
The ADCLK948 features eight full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias V
CC
to the positive supply and V
EE
to ground. For ECL
operation, bias V
CC
to ground and V
EE
to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to V
CC
− 2 V for a total differential
output swing of 1.6 V.
The ADCLK948 is available in a 32-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
V
T
1
CLK1
CLK1
Figure 1.
Rev. B
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08280-001
V
REF
1
ADCLK948
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Determining Junction Temperature .......................................... 5
ESD Caution .................................................................................. 5
Thermal Performance .................................................................. 5
Data Sheet
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Functional Description .....................................................................9
Clock Inputs ...................................................................................9
Clock Outputs ................................................................................9
Clock Input Select (IN_SEL) Settings...................................... 10
PCB Layout Considerations ...................................................... 10
Input Termination Options ....................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
8/2016—Rev. A to Rev. B
Changed CP-32-8 to CP-32-21 .................................... Throughout
Changes to Figure 2 and Table 7 ..................................................... 6
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
6/2010—Rev. 0 to Rev. A
Changed Output Voltage Differential Parameter to Output
Voltage, Single Ended Parameter, Table 1 ..................................... 3
Changes to Output Voltage, Single Ended Parameter, Table 1 ... 3
7/2009—Revision 0: Initial Version
Rev. B | Page 2 of 12
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
ADCLK948
Typical (Typ column) values are given for V
CC
− V
EE
= 3.3 V and T
A
= 25°C, unless otherwise noted. Minimum (Min column) and maximum
(Max column) values are given over the full V
CC
− V
EE
= 3.3 V ± 10% and T
A
= −40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter
DC INPUT CHARACTERISTICS
Input Common Mode Voltage
Input Differential Range
Input Capacitance
Input Resistance
Single-Ended Mode
Differential Mode
Common Mode
Input Bias Current
Hysteresis
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
Output Voltage Low Level
Output Voltage, Single Ended
Reference Voltage
Output Voltage
Output Resistance
Symbol
V
ICM
V
ID
C
IN
Min
V
EE
+ 1.5
0.4
0.4
50
100
50
20
10
V
OH
V
OL
V
O
V
REF
V
CC
− 1.26
V
CC
− 1.99
610
(V
CC
+ 1)/2
235
V
CC
− 0.76
V
CC
− 1.54
960
Typ
Max
V
CC
− 0.1
3.4
Unit
V
V p-p
pF
Ω
Ω
kΩ
µA
mV
V
V
mV
V
Ω
Test Conditions/Comments
±1.7 V between input pins
Open V
T
x
50 Ω to (V
CC
− 2.0 V)
50 Ω to (V
CC
− 2.0 V)
V
OH
− V
OL
, output static
−500 µA to +500 µA
Table 2. Timing Characteristics
Parameter
AC PERFORMANCE
Maximum Output Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Temperature Coefficient
Output-to-Output Skew
1
Part-to-Part Skew
Additive Time Jitter
Integrated Random Jitter
Broadband Random Jitter
2
Crosstalk-Induced Jitter
3
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
f
IN
= 1 GHz
Symbol
Min
4.5
t
R
t
F
t
PD
40
40
175
Typ
4.8
75
75
210
50
9
90
90
245
25
45
Max
Unit
GHz
ps
ps
ps
fs/°C
ps
ps
fs rms
fs rms
fs rms
Test Conditions/Comments
See Figure 4 for differential output voltage vs.
frequency, >0.8 V differential output swing
20% to 80% measured differentially
V
ICM
= 2 V, V
ID
= 1.6 V p-p
V
ID
= 1.6 V p-p
BW = 12 kHz − 20 MHz, CLK = 1 GHz
V
ID
= 1.6 V p-p, 8 V/ns, V
ICM
= 2 V
28
75
90
−119
−134
−145
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns (see Figure 11,
the phase noise plot, for more details)
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
1
2
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3
This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
Rev. B | Page 3 of 12
ADCLK948
Table 3. Input Select Control Pin
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Symbol
V
IH
V
IL
I
IH
I
IL
Min
V
CC
− 0.4
V
EE
Typ
Max
V
CC
1
100
0.6
Data Sheet
Unit
V
V
μA
mA
pF
2
Table 4. Power
Parameter
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
Positive Supply Current
Power Supply Rejection
1
Output Swing Supply Rejection
2
1
2
Symbol
V
CC
− V
EE
I
VEE
I
VCC
PSR
VCC
PSR
VCC
Min
2.97
Typ
Max
3.63
Unit
V
mA
mA
ps/V
dB
Test Conditions/Comments
3.3 V + 10%
Static
V
CC
− V
EE
= 3.3 V ± 10%
V
CC
− V
EE
= 3.3 V ± 10%
V
CC
− V
EE
= 3.3 V ± 10%
V
CC
− V
EE
= 3.3 V ± 10%
96
288
<3
28
120
330
Change in t
PD
per change in V
CC
.
Change in output swing per change in V
CC
.
Rev. B | Page 4 of 12
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
V
CC
− V
EE
Input Voltage
CLK0, CLK1, CLK0, CLK1, IN_SEL
CLK0, CLK1, CLK0, CLK1 to V
T
x Pin (CML,
LVPECL Termination)
CLK0, CLK1 to CLK0, CLK1
Input Termination, V
T
x to CLK0, CLK1, CLK0,
and CLK1
Maximum Voltage on Output Pins
Maximum Output Current
Voltage Reference (V
REF
x)
Operating Temperature Range
Ambient
Junction
Storage Temperature Range
Rating
6V
V
EE
− 0.5 V to
V
CC
+ 0.5 V
±40 mA
±1.8 V
±2 V
V
CC
+ 0.5 V
35 mA
V
CC
to V
EE
−40°C to +85°C
150°C
−65°C to +150°C
ADCLK948
DETERMINING JUNCTION TEMPERATURE
To determine the junction temperature on the application
printed circuit board (PCB), use the following equation:
T
J
=
T
CASE
+ (Ψ
JT
×
P
D
)
where:
T
J
is the junction temperature (°C).
T
CASE
is the case temperature (°C) measured by the customer at
the top center of the package.
Ψ
JT
is from Table 6.
P
D
is the power dissipation.
Values of
θ
JA
are provided for package comparison and PCB
design considerations.
θ
JA
can be used for a first-order approxi-
mation of T
J
by the equation
T
J
=
T
A
+ (
θ
JA
×
P
D
)
where
T
A
is the ambient temperature (°C).
Values of
θ
JB
are provided in Table 6 for package comparison
and PCB design considerations.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
THERMAL PERFORMANCE
Table 6.
Parameter
Junction-to-Ambient Thermal Resistance
Still Air
0 m/sec Air Flow
Moving Air
1 m/sec Air Flow
2.5 m/sec Air Flow
Junction-to-Board Thermal Resistance
Moving Air
1 m/sec Air Flow
Junction-to-Case Thermal Resistance
Moving Air
Die-to-Heatsink
Junction-to-Top-of-Package Characterization Parameter
Still Air
0 m/sec Air Flow
1
Symbol
θ
JA
Description
Per JEDEC JESD51-2
Value
1
Unit
49.8
θ
JMA
Per JEDEC JESD51-6
43.5
39.0
θ
JB
Per JEDEC JESD51-8
30.7
θ
JC
Per MIL-STD 883, Method 1012.1
8.8
Ψ
JT
Per JEDEC JESD51-2
0.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine if they are similar to those assumed in these calculations.
Rev. B | Page 5 of 12
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