HD74HC646/HD74HC648
Octal Bus Transceivers/Registers with Multiplexed 3-state outputs
Description
Six control inputs enable this device to be used as a latched transceiver, unlatched transceiver or a
combination of both. As a latched transceiver, data from one bus is stored for later retrieval by the other
bus. Alternately real time bus data (unlatched) may be directly transferred from one bus to another.
Circuit operation is determined by the Control
G,
Direction, Clock AB, Clock BA, Select AB, Select BA
control inputs. The enable input, Contorl
G,
controls whether any bus outputs are enabled. The direction
control Direction (DIR), determines which bus is enabled, and hence the direction data flows: The Select
AB, Select BA inputs cotrol whether the latched data (stored in D type flip-flops), or the bus data (from
other bus input pins) is transferred. Each set of flip-flops has its own clock Clock AB and Clock BA, for
storing data. Data is latched on the rising edge of the clock.
Features
•
•
•
•
•
High Speed Operation: t
pd
(Bus to Bus) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: I
CC
(static) = 4 µA max (Ta = 25°C)
京公网安备 11010802033920号
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