Impact Definition: Each erratum is marked with an impact, as defined below:
Minor—Workaround exists.
Major—Errata that do not conform to the data sheet or standard.
Information—The device behavior is not ideal but acceptable. Typically, the data sheet will be
changed to match the device behavior.
Errata Details
1.
Description:
The output impedance of the drivers on the USB D+ and D- data lines is nominally 28
but, in some cases, may be as low as 26
.
The minimum USB specification for full-speed devices on
the D+ and D- data lines is 28
.
Impact:
This may impact systems that need to be submitted for USB compliance testing. The
specification for USB compliance is a system-level parameter, not a chip-level parameter. In most
systems, the lower impedance of the device will not be a factor. A typical PCB will add 2-3
to the
effective driver impedance and bring the system level impedance within specifications.
Workaround:
For systems that require USB certification, it is recommended to add some series
impedance (between 5 and 8 Ohms, ¼ watt or higher) to D+ and D- in the PCB design.
2.
Description:
The GPIO signals will be driven low for approximately 40 microseconds after power cycling
the device and then return to the configured reset state.
400 West Cesar Chavez, Austin, TX 78701 (512) 416-8500 FAX (512) 416-9669 www.silabs.com
C8051T620-1_T320-1-2-3ERD_T626-7ERB073112
Impact:
This may impact systems where the T62x/T32x is connected to devices that are powered from a
separate supply and turned on before the T62x/T32x receives power through the 5 volt regulator or
through VDD and VIO pins. The drop of the T62x/T32x signals may be seen as invalid data to the
connected devices.
Workaround:
In systems that are affected by this drop, the T62x/T32x should be powered through the 5
volt regulator or through the VDD and VIO pins from the same supply used by devices that are
connected to the GPIO signals of the T62x/T32x.
3.
Description:
The system clock frequency cannot be set to 48 MHz before entering Suspend Mode.
Setting the system clock to high frequencies can cause improper code execution after exit from suspend
on some devices.
Impact:
Devices exhibiting the issue can fail to enumerate properly over USB after exit from Suspend
Mode.
Workaround:
The internal high-frequency oscillator should be set to output 1.5 MHz (OSCICN register,
IFCN[1:0] = 00b) and the system clock should be set to be derived from this oscillator (CLKSEL register,
CLKSL[2:0] = 000b) before entering Suspend Mode by setting the SUSPEND bit in the OSCICN register.
400 West Cesar Chavez, Austin, TX 78701 (512) 416-8500 FAX (512) 416-9669 www.silabs.com
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
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