CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to +100µA.
2.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
ANALOG
(Notes 3, 4)
Zero Input Reading
Ratiometric Error (Note 4)
V+ = +5V, V- = -5V, T
A
= 25
o
C, f
CLK
Set for 3 Readings/s, Unless Otherwise Specified
TEST CONDITIONS
MIN
-00000
-3
-
-
-
-
-
-
-
TYP
+00000
0
0.5
0.01
0.5
15
1
0.5
2
MAX
+00000
+3
1
-
1
-
10
2
5
UNITS
Counts
Counts
LSB
LSB
LSB
µV
pA
µV/
o
C
ppm/×
o
C
PARAMETER
V
lN
= 0V, V
REF
= 1.000V
V
lN
= V
REF
= 1.000V
-2V
≤
V
IN
≤
+2V
-2V
≤
V
IN
≤
+2V
-V
lN
≡
+V
lN
≈
2V
V
lN
= 0V, Full scale = 2.000V
V
lN
= 0V
V
lN
= 0V, 0
o
C to 70
o
C
V
lN
= +2V, 0
o
C to 70
o
C
Ext. Ref. 0ppm/
o
C
Linearity Over
±
Full Scale (Error of Reading from Best Straight Line)
Differential Linearity (Difference Between Worse Case Step of
Adjacent Counts and Ideal Step)
Rollover Error (Difference in Reading for Equal Positive and
Negative Voltage Near Full Scale)
Noise (Peak-to-Peak Value Not Exceeded 95% of Time), e
N
Input Leakage Current, I
ILK
Zero Reading Drift (Note 7)
Scale Factor Temperature Coefficient, T
C
(Notes 5 and 7)
DIGITAL INPUTS
Clock In, Run/Hold (See Figure 2)
V
INH
V
INL
I
INL
I
INH
DIGITAL OUTPUTS
All Outputs, V
OL
B1 , B2 , B4 , B8 , D1 , D2 , D3 , D4 , D5 , V
OH
BUSY, STROBE, OVERRANGE, UNDERRANGE, POLARITY, V
OH
SUPPLY
+5V Supply Range, V+
-5V Supply Range, V-
+5V Supply Current, I+
-5V Supply Current, I-
Power Dissipation Capacitance, C
PD
CLOCK
Clock Frequency (Note 6)
2.8
-
V
IN
= 0V
V
IN
= +5V
I
OL
= 1.6mA
I
OH
= -1mA
I
OH
= -10µA
-
-
-
2.4
4.9
+4
-3
f
C
= 0
f
C
= 0
vs Clock Frequency
-
-
-
DC
2.2
1.6
0.02
0.1
0.25
4.2
4.99
+5
-5
1.1
0.8
40
2000
-
0.8
0.1
10
0.40
-
-
+6
-8
3.0
3.0
-
1200
V
V
mA
µA
V
V
V
V
V
mA
mA
pF
kHz
NOTES:
3. Tested in 4
1
/
2
digit (20.000 count) circuit shown in Figure 3. (Clock frequency 120kHz.)
4. Tested with a low dielectric absorption integrating capacitor, the 27Ω INT OUT resistor shorted, and R
lNT
= 0. See Component Value Selection Discussion.
5. The temperature range can be extended to 70
o
C and beyond as long as the auto-zero and reference capacitors are increased to absorb the higher leakage
of the ICL7135.
6. This specification relates to the clock frequency range over which the lCL7135 will correctly perform its various functions See “Max Clock Frequency”
section for limitations on the clock frequency range in a system.
7. Parameter guaranteed by design or characterization. Not production tested.
3
FN3093.3
ICL7135
SET V
REF
= 1.000V
ICL7135
V
REF
IN
100kΩ
ANALOG
GND
100kΩ
-5V
1 V-
2 REF
UNDERRANGE 28
OVERRANGE 27
3 ANALOG GND STROBE 26
0.47µF
1µF
100kΩ
1µF
4 INT OUT
27Ω
5 A-Z IN
6 BUF OUT
RUN/HOLD 25
DIGITAL GND 24
POLARITY 23
0V
CLOCK
IN
120kHz
V
+
7 REF CAP 1 CLOCK IN 22
8 REF CAP 2
9 IN LO-
10 IN HI+
11 V+
12 MSD D5
13 LSB B1
14 B2
BUSY 21
LSD DI 20
D2 19
D3 18
D4 17
MSB B8 16
B4 15
SIGNAL
INPUT
100K
0.1µF
+5V
PAD
DIG GND
FIGURE 1. ICL7135 TEST CIRCUIT
FIGURE 2. ICL7135 DIGITAL LOGIC INPUT
C
REF
C
REF+
8
REF HI
2
C
REF
7
R
INT
BUFFER
6
V
+
11
C
AZ
AUTO
ZERO
5
INTEGRATOR
C
INT
INT
4
+
INPUT
HIGH
+
AZ
COMPARATOR
ZI
A/Z
AZ
3
ANALOG
COMMON
9
INT
DE(+)
DE(-)
INPUT
LOW
POLARITY
F/F
-
-
+
AZ
IN HI
10
INT
DE(-)
DE(+)
ZERO-
CROSSING
DETECTOR
A/Z, DE(±), ZI
1
V
-
IN LO
FIGURE 3. ANALOG SECTION OF ICL7135
4
FN3093.3
ICL7135
Detailed Description
Analog Section
Figure 3 shows the Block Diagram of the Analog Section for
the ICL7135. Each measurement cycle is divided into four
phases. They are (1) auto-zero (AZ), (2) signal-integrate
(INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).
Auto-Zero Phase
During auto-zero, three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor C
AZ
to compensate
for offset voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop, the
AZ accuracy is limited only by the noise of the system. In any
case, the offset referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO for a
fixed time. This differential voltage can be within a wide
common mode range; within one volt of either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog COMMON
to establish the correct common-mode voltage. At the end of
this phase, the polarity of the integrated signal is latched into
the polarity F/F.
De-Integrate Phase
The third phase is de-integrate or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the inte-
grator output to return to zero. The time required for the out-
put to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:
V
IN
-
OUTPUT COUNT
=
10,000
--------------
.
V
REF
However, since the integrator also swings with the common
mode voltage, care must be exercised to assure the integrator
output does not saturate. A worst case condition would be a
large positive common-mode voltage with a near full scale
negative differential input voltage. The negative input signal
drives the integrator positive when most of its swing has been
used up by the positive common mode voltage. For these
critical applications the integrator swing can be reduced to
less than the recommended 4V full scale swing with some
loss of accuracy. The integrator output can swing within 0.3V
of either supply without loss of linearity.
Analog COMMON
Analog COMMON is used as the input low return during auto-
zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system and
is taken care of by the excellent CMRR of the converter.
However, in most applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The reference voltage is referenced to analog
COMMON.
Reference
The reference input must be generated as a positive voltage
with respect to COMMON, as shown in Figure 4.
V+
REF HI
ICL7135
6.8V
ZENER
COMMON
I
Z
V-
FIGURE 4A.
Zero Integrator Phase
The final phase is zero integrator. First, input low is shorted
to analog COMMON. Second, a feedback loop is closed
around the system to input high to cause the integrator
output to return to zero. Under normal condition, this phase
lasts from 100 to 200 clock pulses, but after an overrange
conversion, it is extended to 6200 clock pulses.
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier; or specifically
from 0.5V below the positive supply to 1V above the negative
supply. In this range the system has a CMRR of 86dB typical.
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