Data Sheet
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 2.5 GHz in baseband mode
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
1.5 GHz to 7.5 GHz in Mix-Mode
Bypassable interpolation
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
Fast frequency hopping
16-Bit, 12 GSPS,
RF DAC and Direct Digital Synthesizer
AD9164
When combined with a 100 MHz serial peripheral interface (SPI)
and fast hop modes, phase coherent fast frequency hopping (FFH)
is enabled, with several modes to support multiple applications.
In baseband mode, wide analog bandwidth capability combines
with high dynamic range to support DOCSIS 3.1 cable infrastruc-
ture compliance from the minimum of one carrier up to the full
maximum spectrum of 1.791 GHz of signal bandwidth. A 2×
interpolator filter (FIR85) enables the
AD9164
to be configured
for lower data rates and converter clocking to reduce the overall
system power and ease the filtering requirements. In Mix-Mode™
operation, the
AD9164
can reconstruct RF carriers in the second
and third Nyquist zones up to 7.5 GHz while still maintaining
exceptional dynamic range. The output current can be programmed
from 8 mA to 38.76 mA. The
AD9164
data interface consists of
up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
An SPI interface configures the
AD9164
and monitors the status of
all registers. The
AD9164
is offered in a 165-ball, 8 mm × 8 mm,
0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm × 11 mm,
0.8 mm pitch, CSP_BGA package, including a leaded ball option.
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 CMTS/ video on demand (VOD)/edge
quadrature amplitude modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
The
AD9164
is a high performance, 16-bit digital-to-analog
converter (DAC) and direct digital synthesizer (DDS) that
supports update rates to 6 GSPS. The DAC core is based on a
quad-switch architecture coupled with a 2× interpolator filter
that enables an effective DAC update rate of up to 12 GSPS in
some modes. The high dynamic range and bandwidth makes
these DACs ideally suited for the most demanding high speed
radio frequency (RF) DAC applications.
1
PRODUCT HIGHLIGHTS
1.
2.
3.
High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
Bandwidth and dynamic range to meet DOCSIS 3.1
compliance and multiband wireless communications
standards with margin.
ISET VREF
The DDS consists of a bank of 32, 32-bit numerically controlled
oscillators (NCOs), each with its own phase accumulator.
FUNCTIONAL BLOCK DIAGRAM
RESET
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
HB
2×
HB
3×
HB
2×,
4×,
8×
TO JESD
TO DATAPATH
JESD
NCO
DATA
LATCH
IRQ
SPI
AD9164
VREF
NRZ RZ MIX
HB
2×
INV
SINC
DAC
CORE
OUTPUT±
CLOCK
DISTRIBUTION
14414-001
TX_ENABLE
CLK±
Figure 1.
1
Protected by U.S. Patents 6,842,132 and 7,796,971.
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Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Technical Support
www.analog.com
AD9164
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
DAC Input Clock Overclocking Specifications ........................ 5
Power Supply DC Specifications ................................................ 5
Serial Port and CMOS Pin Specifications ................................. 7
JESD204B Serial Interface Speed Specifications ...................... 8
SYSREF± to DAC Clock Timing Specifications ....................... 8
Digital Input Data Timing Specifications ................................. 9
JESD204B Interface Electrical Specifications ........................... 9
AC Specifications........................................................................ 10
Absolute Maximum Ratings .......................................................... 11
Reflow Profile .............................................................................. 11
Thermal Management ............................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Static Linearity ............................................................................ 16
AC Performance (NRZ Mode) ................................................. 17
AC (Mix-Mode) .......................................................................... 22
DOCSIS Performance (NRZ Mode) ........................................ 25
Terminology .................................................................................... 30
Theory of Operation ...................................................................... 31
Serial Port Operation ..................................................................... 32
Data Format ................................................................................ 32
Serial Port Pin Descriptions ...................................................... 32
Serial Port Options ..................................................................... 32
Data Sheet
JESD204B Serial Data Interface .................................................... 34
JESD204B Overview .................................................................. 34
Physical Layer ............................................................................. 35
Data Link Layer .......................................................................... 38
Transport Layer .......................................................................... 46
JESD204B Test Modes ............................................................... 48
JESD204B Error Monitoring..................................................... 50
Hardware Considerations ......................................................... 52
Main Digital Datapath ................................................................... 53
Data Format ................................................................................ 53
Interpolation Filters ................................................................... 53
Digital Modulation ..................................................................... 56
Inverse Sinc ................................................................................. 58
Downstream Protection ............................................................ 59
Datapath PRBS ........................................................................... 59
Datapath PRBS IRQ ................................................................... 60
Interrupt Request Operation ........................................................ 61
Interrupt Service Routine .......................................................... 61
Applications Information .............................................................. 62
Hardware Considerations ......................................................... 62
Analog Interface Considerations.................................................. 65
Analog Modes of Operation ..................................................... 65
Clock Input.................................................................................. 66
Shuffle Mode ............................................................................... 67
DLL............................................................................................... 67
Voltage Reference ....................................................................... 67
Temperature Sensor ................................................................... 67
Analog Outputs .......................................................................... 68
Start-Up Sequence .......................................................................... 71
Register Summary .......................................................................... 73
Register Details ............................................................................... 82
Outline Dimensions ..................................................................... 137
Ordering Guide ........................................................................ 138
Rev. C | Page 2 of 138
Data Sheet
REVISION HISTORY
7/2017—Rev. B to Rev. C
Changes to Table 45 ........................................................................78
Changes to Table 46 ......................................................................126
6/2017—Rev. A to Rev. B
Added Fast Frequency Hopping to Features Section ................... 1
Change to Figure 101 ......................................................................41
Change to Table 30 ..........................................................................49
1/2017—Rev. 0 to Rev. A
Deleted DLL_VDD_1P2 Parameter, Table 1 .....................................4
Added Temperature Sensor Parameter, Table 1 ................................4
Change to Endnote 1, Table 1 .................................................................4
Change to OUTPUT± to VNEG_N1P2 Parameter, Table 10 ....11
Changes to Link Delay Setup Example, With Known Delays
Section .......................................................................................................... 43
AD9164
Changes to Link Delay Setup Example, Without Known Delay
Section ...........................................................................................................45
Changes to Table 24 .................................................................................46
Added Datapath PRBS Section ..................................................... 59
Added Datapath PRBS IRQ Section ............................................. 60
Moved Figure 135 .....................................................................................67
Added Temperature Sensor Section.......................................................68
Changes to Equivalent DAC Output and Transfer Function
Section ..........................................................................................................68
Changes to Output Stage Configuration Section and Figure 142
Caption ..........................................................................................................69
Added Register 0x132 Row to Register 0x135 Row, Table 45 ... 74
Added Register 0x132 Row to Register 0x135 Row, Table 46 ... 91
Change to Register 0x230............................................................... 93
7/2016—Revision 0: Initial Version
Rev. C | Page 3 of 138
AD9164
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (I
OUTFS
) = 40 mA, and T
A
= −40°C to
+85°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DAC Update Rate
Minimum
Maximum
Adjusted
4
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Input Power
Common-Mode Voltage
Input Impedance
1
TEMPERATURE DRIFT
Gain
Reference Voltage
TEMPERATURE SENSOR
Accuracy
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
VDD25_DAC
VDD12A
2
VDD12_CLK
2
VNEG_N1P2
DIGITAL SUPPLY VOLTAGES
DVDD
IOVDD
3
SERDES SUPPLY VOLTAGES
VDD_1P2
VTT_1P2
DVDD_1P2
PLL_LDO_VDD12
PLL_CLK_VDD12
SYNC_VDD_3P3
BIAS_VDD_1P2
1
2
Test Conditions/Comments
Min
16
Typ
Max
Unit
Bit
GSPS
GSPS
GSPS
GSPS
LSB
LSB
%
1.5
VDDx = 1.3 V ± 2%
VDDx
1
= 1.3 V ± 2%
2
, FIR85
3
2× interpolator enabled
VDDx
1
= 1.3 V ± 2%
2
1
2
6
12
6
6.4
12.8
6.4
±2.7
±1.7
−1.7
R
SET
= 9.76 kΩ
R
SET
= 9.76 kΩ
R
LOAD
= 90 Ω differential on-chip
AC-coupled
3 GSPS input clock
7.37
35.8
−20
8
38.76
0
0.6
90
105
75
8.57
41.3
+10
mA
mA
dBm
V
Ω
ppm/°C
ppm/°C
%
V
After single point calibration (See the
Temperature Sensor
section)
±5
1.19
2.375
1.14
1.14
−1.26
2.5
1.2
1.2
−1.2
1.2
2.5
1.2
1.2
1.2
1.2
1.2
3.3
1.2
2.625
1.326
1.326
−1.14
1.326
3.465
1.326
1.326
1.326
1.326
1.326
3.465
1.326
V
V
V
V
V
V
V
V
V
V
V
V
V
Includes VDD12_DCD/DLL
1.14
1.71
1.14
1.14
1.14
1.14
1.14
3.135
1.14
Can connect to VDD_1P2
Can connect to PLL_LDO_VDD12
Can connect to VDD_1P2
See the Clock Input section for more details.
For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.
3
IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
4
The adjusted DAC update rate is calculated as f
DAC
divided by the minimum required interpolation factor. For the
AD9164,
the minimum interpolation factor is 1.
Therefore, with f
DAC
= 6 GSPS, f
DAC
adjusted = 6 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, f
DAC
= 2 × (DAC clock input frequency), and the
minimum interpolation increases to 2× (interpolation value). Thus, for the
AD9164,
with FIR85 enabled and DAC clock = 6 GSPS, f
DAC
= 12 GSPS, minimum interpolation = 2×, and
the adjusted DAC update rate = 6 GSPS.
Rev. C | Page 4 of 138
Data Sheet
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
AD9164
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, I
OUTFS
= 40 mA, T
A
= −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperature and voltage conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature that does not
exceed 105°C to avoid damage to the device. See Table 10 for details on maximum junction temperature permitted for certain clock
speeds.
Table 2.
Parameter
1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
Test Conditions/Comments
T
JMAX
= 25°C
T
JMAX
= 85°C
T
JMAX
= 105°C
T
JMAX
= 25°C
T
JMAX
= 85°C
T
JMAX
= 105°C
T
JMAX
= 25°C
T
JMAX
= 85°C
T
JMAX
= 105°C
Min
6.0
5.6
5.4
6.1
5.8
5.6
6.4
6.2
6.0
Typ
Max
Unit
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
1
T
JMAX
is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
I
OUTFS
= 40 mA, T
A
= −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 2× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD
1
= 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD
1
= 2.5 V
Test Conditions/Comments
NCO on, FIR85 on
Min
Typ
Max
Unit
−119
Includes VDD12_DCD/DLL
93.8
3.7
229
−112
621.3
2.5
425.5
62
84.4
9.3
100
150
279
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
971
2.7
550
86
106
11
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 on
93.8
3.7
228.7
−120.7
Includes VDD12_DCD/DLL
598.4
2.5
mA
µA
mA
mA
mA
mA
Rev. C | Page 5 of 138
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