JESD-204A-E3-UT datasheet, PDF

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JESD-204A-E3-UT: DescriptionDevelopment Software JESD204A for LatticeECP3 - Site License; CategoryDevelopment board/suite/development tools; File Size3MB，39 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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Development Software JESD204A for LatticeECP3 - Site License

JESD-204A-E3-UT Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Lattice
Product Category	Development Software
RoHS	Details
Product	IP Core - JESD204B
For Use With	Lattice ECP3
Factory Pack Quantity	1

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JESD204B IP Core

User Guide

FPGA-IPUG-02010 Version 2.3

June 2017

JESD204B IP Core

User Guide

Contents

Introduction .................................................................................................................................................................. 4

1.1.

Quick Facts .......................................................................................................................................................... 4

1.2.

Features ............................................................................................................................................................... 5

1.3.

What is Not Supported ........................................................................................................................................ 5

1.4.

Conventions......................................................................................................................................................... 6

1.5.

Data Ordering and Data Types ............................................................................................................................ 6

1.6.

Signal Names ....................................................................................................................................................... 6

2. Functional Description .................................................................................................................................................. 7

2.1.

Rx Core ................................................................................................................................................................ 7

2.2.

Tx Core............................................................................................................................................................... 14

3. Parameter Settings ..................................................................................................................................................... 19

3.1.

Configuring JESD204B Core in IPexpress ........................................................................................................... 19

3.2.

Configuring JESD204B Core in Clarity Designer ................................................................................................. 21

4. IP Core Generation and Evaluation ............................................................................................................................. 22

4.1.

Licensing the IP .................................................................................................................................................. 22

4.2.

Getting Started .................................................................................................................................................. 22

4.3.

Creating IP in Clarity Designer ........................................................................................................................... 23

4.4.

Generating IP in IPexpress................................................................................................................................. 27

4.5.

Generated IP Directory Structure and Files ....................................................................................................... 28

4.6.

Instantiating the IP Core .................................................................................................................................... 29

4.7.

Running Functional Simulation ......................................................................................................................... 30

4.7.1. Running Functional Simulation in ModelSim ...............................................................................................30

4.7.2. Running Functional Simulation in Active HDL ..............................................................................................30

4.8.

Simulation Strategies ........................................................................................................................................ 31

4.9.

Simulation Environment .................................................................................................................................... 31

4.10. Synthesizing and Implementing the IP in a Top-Level Design ........................................................................... 32

4.11. Hardware Evaluation ......................................................................................................................................... 32

4.11.1. Enabling Hardware Evaluation in Diamond ..................................................................................................32

4.12. Updating/Regenerating the IP........................................................................................................................... 32

4.12.1. Regenerating an IP in Clarity Designer .........................................................................................................32

5. Application Support .................................................................................................................................................... 34

References .......................................................................................................................................................................... 35

Technical Support Assistance ............................................................................................................................................. 35

Appendix A. Resource Utilization ....................................................................................................................................... 36

LatticeECP3-70 Utilization .............................................................................................................................................. 36

LFE5UM-85 Utilization .................................................................................................................................................... 36

LFE5UM5G-85 Utilization ................................................................................................................................................ 36

Appendix B. Limitations ...................................................................................................................................................... 37

JESD204B 5G IP Core ....................................................................................................................................................... 37

Revision History .................................................................................................................................................................. 38

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02010-2.3

JESD204B IP Core

User Guide

Figures

Figure 2.1. JESD204B Rx IP Core I/O ..................................................................................................................................... 7

Figure 2.2. JESD204B Single Device Application ................................................................................................................. 10

Figure 2.3. JESD204B IP Receiver Functions ....................................................................................................................... 11

Figure 2.4. JESD204B Rx 3G IP Core Block Diagram ............................................................................................................ 11

Figure 2.5. JESD204B Rx 3G IP Core Block Lane Alignment Status ..................................................................................... 12

Figure 2.6. JESD204B Rx 3G IP Core User Interface ............................................................................................................ 12

Figure 2.7. JESD204B Tx IP Core I/O Ports .......................................................................................................................... 14

Figure 2.8. JESD204B Tx 5G IP Core Block Diagram ............................................................................................................ 17

Figure 3.1. Global Tab ......................................................................................................................................................... 20

Figure 3.2. Others Tab ........................................................................................................................................................ 20

Figure 3.3. PCS Tab ............................................................................................................................................................. 21

Figure 4.1. Clarity Designer Window .................................................................................................................................. 22

Figure 4.2. Starting Clarity Designer from Diamond Design Environment ......................................................................... 23

Figure 4.3. Configuring JESD204B IP in Clarity Designer ..................................................................................................... 24

Figure 4.4. JESD204B 5G IP Configuration Interface in Clarity Designer ............................................................................ 25

Figure 4.5. Configuring PCS in JESD204B 5G IP Configuration Interface in Clarity Designer .............................................. 25

Figure 4.6. Place and Generate JESD204B IP in Clarity Designer ........................................................................................ 26

Figure 4.7. Configuration Interface ..................................................................................................................................... 27

Figure 4.8. JESD204B Core Directory Structure .................................................................................................................. 28

Figure 4.9. Simulation Environment Block Diagram ........................................................................................................... 31

Figure 4.10. Data Patterns Seen on User Interface in Simulation ...................................................................................... 31

Figure 4.11. IP Regeneration in Clarity Designer ................................................................................................................ 33

Figure 5.1. HetNet and Small Cells Application .................................................................................................................. 34

Tables

Table 1.1. JESD204B 3G IP Core Quick Facts ......................................................................................................................... 4

Table 1.2. JESD204B 5G IP Core Quick Facts ......................................................................................................................... 5

Table 2.1. Rx IP Core Pin Function Description ..................................................................................................................... 7

Table 2.2. Frame Boundary versus Octet Data at Rx User Interface for 3G IP Core (F=3) .................................................. 12

Table 2.3. Frame Boundary versus Octet Data at Rx User Interface for 5G IP Core (F=3) .................................................. 13

Table 2.4. Tx IP Core Pin Function Description ................................................................................................................... 14

Table 2.5. Frame Boundary versus Octet Data at Rx User Interface for 3G IP Core (F=3) .................................................. 17

Table 2.6. Frame Boundary versus Octet Data at Rx User Interface for 3G IP Core (F=3) .................................................. 18

Table 3.1. JESD20B IP Core Parameters .............................................................................................................................. 19

Table 4.1. Files Generated in Clarity Designer .................................................................................................................... 28

Table A.1. Resource Utilization ........................................................................................................................................... 36

Table A.2. Resource Utilization ........................................................................................................................................... 36

Table A.3. Resource Utilization ........................................................................................................................................... 36

Table B.1. Core and Reference Design Minimum Device Support...................................................................................... 37

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02010-2.3

JESD-204A-E3-UT Related Products

	JESD-204A-E3-UT	JESD-204B-E5-U
Description	Development Software JESD204A for LatticeECP3 - Site License	Development software JESD204B FOR ECP5 - SINGLE DESIGN LICENSE
Product Category	Development Software	develop software

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