Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 6
XAUI IP Core I/O................................................................................................................................................... 9
Functional Description......................................................................................................................................... 10
XGMII and Slip Buffers............................................................................................................................... 14
XAUI-to-XGMII Translation (Receive Interface) ......................................................................................... 15
XGMII-to-XAUI Translation (Transmit Interface) ........................................................................................ 16
Management Data Input/Output (MDIO) Interface (Optional) .................................................................... 18
Management Frame Structure ................................................................................................................... 19
Register Descriptions .......................................................................................................................................... 20
Input/Output Timing............................................................................................................................................. 22
XGMII Specifications.................................................................................................................................. 22
XAUI Specifications.................................................................................................................................... 24
MDIO Specifications................................................................................................................................... 24
XAUI IP Configuration Dialog Box....................................................................................................................... 25
Parameter Descriptions....................................................................................................................................... 25
Tx Slip Buffer.............................................................................................................................................. 25
Rx Slip Buffer ............................................................................................................................................. 25
MDIO.......................................................................................................................................................... 25
Chapter 3. Parameter Settings ............................................................................................................ 25
Licensing the IP Core.......................................................................................................................................... 26
IPexpress IP Generation Flow ............................................................................................................................ 26
Getting Started ........................................................................................................................................... 26
Chapter 4. IP Core Generation............................................................................................................. 26
IPexpress-Created Files and Top Level Directory Structure............................................................................... 28
Instantiating the Core ................................................................................................................................. 30
Running Functional Simulation .................................................................................................................. 30
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 31
Clarity Designer IP Generation Flow................................................................................................................... 32
Getting Started ........................................................................................................................................... 32
Configuring and Placing the IP Core.......................................................................................................... 34
Generating the IP Core .............................................................................................................................. 36
Clarity Designer-Created Files and Top Level Directory Structure ..................................................................... 37
Instantiating the Core ................................................................................................................................. 38
Running Functional Simulation .................................................................................................................. 39
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 39
Hardware Evaluation........................................................................................................................................... 40
Enabling Hardware Evaluation in Diamond................................................................................................ 40
Updating/Regenerating the IP Core .................................................................................................................... 40
Regenerating an IP Core in Diamond ........................................................................................................ 40
Regenerating an IP Core using Clarity Designer ....................................................................................... 41
Lattice Technical Support.................................................................................................................................... 42
References.......................................................................................................................................................... 42
LatticeECP3 ............................................................................................................................................... 42
ECP5.......................................................................................................................................................... 42
Revision History .................................................................................................................................................. 42
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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LatticeECP3 and ECP5 XAUI IP Core User Guide
Chapter 1:
Introduction
The 10Gb Ethernet Attachment Unit Interface (XAUI) IP Core User’s Guide for the LatticeECP3™ and ECP5™
FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII)
devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together
with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.
The XAUI IP core package comes with the following documentation and files:
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core
The XAUI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of
the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the pur-
chase on an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Details for
using the hardware evaluation capability are described in the Hardware Evaluation section of this document.
Quick Facts
Table 1-1
gives quick facts about the XAUI IP core.
Table 1-1. XAUI IP Core Quick Facts
XAUI IP Configuration
Across All IP configurations
FPGA Families Supported
Core Requirements
Minimal Device Supported
Data Path Width
LUTs
Resource Utilization
sysMEM EBRs
Registers
Lattice Implementation
Synthesis
Design Tool Support
Simulation
Mentor Graphics ModelSim™ SE 10.0
Lattice Synthesis Engine™ (For ECP5 only)
Aldec
®
Active-HDL™ 9.1 Lattice Edition
0-4
1400-3100
Diamond
®
3.3
Synopsys
®
Synplify™ Pro for Lattice F-2014.03L-SP1 beta
0-4
1600-3300
LFE3-17EA-7FTN256C
72 bits
2000-2700
LFE5UM-45F-7BG381C
72 bits
2200-3100
Lattice ECP3, ECP5 (LFE5UM-45F and LFE5UM-85F)
Features
• XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the
LatticeECP3 and ECP5, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encod-
ing/decoding.
• Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP3 and ECP5 FPGA.
• Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3-2005, including:
– 10 GbE Media Independent Interface (XGMII).
– Optional slip buffers for clock domain transfer to/from the XGMII interface.
– Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle,
IPUG115_1.0, April 2015
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LatticeECP3 and ECP5 XAUI IP Core User Guide
Embedded System
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