Data Sheet
FEATURES
Ultralow noise: 0.95 nV/√Hz, 2.6 pA/√Hz
Ultralow distortion
2
nd
harmonic R
L
= 1 kΩ , G = +2
−92 dB at 10 MHz
3
rd
harmonic R
L
= 1 kΩ , G = +2
−105 dB at 10 MHz
High speed
Gain bandwidth product (GBWP): 3.8 GHz
−3 dB bandwidth
700 MHz (G = +2)
550 MHz (G = +10)
Slew rate
475 V/µs (G = +2)
1350 V/µs (G = +10)
New pinout
Custom external compensation, gain range –1, +2 to +10
Supply current: 15 mA
Offset voltage: 0.5 mV max
Wide supply voltage range: 5 V to 12 V
Ultralow Distortion, High Speed,
0.95 nV/√Hz Voltage Noise Op Amp
AD8099
CONNECTION DIAGRAMS
AD8099
TOP VIEW
(Not to Scale)
DISABLE 1
FEEDDBACK 2
–IN 3
+IN 4
8 +V
S
7 V
OUT
6 C
C
5 –V
S
04511-0-001
04511-0-002
NOTES
1. SOLDER THE EXPOSED PADDLE
TO THE GROUND PLANE.
Figure 1. 8-Lead LFCSP (CP-8-13)
AD8099
TOP VIEW
(Not to Scale)
FEEDBACK
1
–IN
2
+IN
3
–V
S 4
8
7
6
5
DISABLE
+V
S
V
OUT
C
C
NOTES
1. SOLDER THE EXPOSED PADDLE
TO THE GROUND PLANE.
Figure 2. 8-Lead SOIC-EP (RD-8-1)
APPLICATIONS
Preamplifiers
Receivers
Instrumentation
Filters
Intermediate frequency (IF) and baseband amplifiers
Analog-to-digital drivers
Digital-to-analog converter (DAC) buffers
Optical electronics
The
AD8099
drives 100 Ω loads at breakthrough performance
levels with only 15 mA of supply current. With the wide supply
voltage range (5 V to 12 V), low offset voltage (0.1 mV typ), wide
bandwidth (700 MHz for G = +2), and a GBWP up to 3.8 GHz,
the
AD8099
is designed to work in a wide variety of applications.
The
AD8099
is available in a 3 mm × 3 mm lead frame chip scale
package (LFCSP) with a new pinout that is specifically optimized
for high performance, high speed amplifiers. The new LFCSP and
pinout enable the breakthrough performance that previously was
not achievable with amplifiers. The
AD8099
is rated to work
over the extended industrial temperature range, −40°C to +125°C.
G = +2
V
= 2V p-p
–50 V
OUT
±5V
S
=
R
L
= 1kΩ
–60
–70
–80
–90
–100
–110
–120
–130
0.1
–40
GENERAL DESCRIPTION
The
AD8099
is an ultralow noise (0.95 nV/√Hz) and distortion
(–92 dBc at 10 MHz) voltage feedback op amp, the combination
of which makes it ideal for 16- and 18-bit systems. The
AD8099
features a new, highly linear, low noise input stage that increases
the full power bandwidth (FPBW) at low gains with high slew
rates. The Analog Devices, Inc., proprietary next generation
extra fast complimentary bipolar (XFCB) process enables such
high performance amplifiers with relatively low power.
The
AD8099
features external compensation, which lets the user
set the gain bandwidth product. External compensation allows
gains from +2 to +10 with minimal trade-off in bandwidth. The
AD8099
also features an extremely high slew rate of 1350 V/µs,
giving the designer flexibility to use the entire dynamic range
without trading off bandwidth or distortion. The
AD8099
settles to 0.1% in 18 ns and recovers from overdrive in 50 ns.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
HARMONIC DISTORTION (dBc)
1.0
FREQUENCY (MHz)
10.0
Figure 3. Harmonic Distortion vs. Frequency and Gain (SOIC)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
04511-A-013
SOLID LINE – SECOND HARMONIC
DOTTED LINE – THIRD HARMONIC
AD8099
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagrams ...................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Specifications with ±5 V Supply ................................................. 3
Specifications with +5 V Supply ................................................. 4
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 15
Applications Information .............................................................. 16
Data Sheet
Using the AD8099 ...................................................................... 16
Circuit Components .................................................................. 16
Recommended Values ............................................................... 17
Circuit Configurations .............................................................. 17
Performance vs. Component Values........................................ 19
Total Output Noise Calculations and Design ......................... 21
Input Bias Current and DC Offset ........................................... 21
DISABLE Pin and Input Bias Cancellation............................. 21
16-Bit ADC Driver ..................................................................... 22
Circuit Considerations .............................................................. 23
Design Tools and Technical Support ....................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/2016—Rev. D to Rev. E
Changed CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Figure 67 ...................................................................... 19
Added Figure 68 to Figure 70; Renumbered Sequentially ........ 19
Changes to Figure 71 ...................................................................... 20
Added Figure 72 and Figure 73..................................................... 20
Changes to PCB Layout Section ................................................... 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide ......................................................... 24
8/2013—Rev. C to Rev. D
Changes to Figure 42 Caption....................................................... 12
Changes to Figure 49 ...................................................................... 13
Changes to Ordering Guide .......................................................... 25
1/2013—Rev. B to Rev. C
Added EPAD Note to Figure 1 and Figure 2 ................................. 1
Changes to PCB Layout Section and Design Tools and
Technical Support Section ............................................................. 23
Deleted Figure 72, Figure 73, Evaluation Boards Section,
and Table 7 ....................................................................................... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 26
6/2004—Rev. A to Rev. B
Change to General Description Section .........................................1
Changes to Maximum Power Dissipation Section........................5
Changes to Applications Section ................................................. 16
Changes to Table 7.......................................................................... 24
Changes to Ordering Guide .......................................................... 26
1/2004—Rev. 0 to Rev. A
Inserted Figure 3 ................................................................................1
Changes to Specifications Section ...................................................3
Inserted Figure 22 to Figure 34........................................................8
Inserted Figure 51 to Figure 55..................................................... 14
Changes to Theory of Operation Section.................................... 16
Changes to Circuit Components Section .................................... 17
Changes to Table 4.......................................................................... 18
Changes to Figure 60...................................................................... 18
Changes to Total Output Noise Calculations and
Design Section ................................................................................ 21
Changes to Figure 60...................................................................... 22
Changes to Figure 62...................................................................... 23
Changes to 16-Bit ADC Driver Section ...................................... 23
Changes to Table 6.......................................................................... 23
Additions to PCB Layout Section................................................. 23
11/2003—Revision 0: Initial Version
Rev. E | Page 2 of 26
Data Sheet
SPECIFICATIONS
SPECIFICATIONS WITH ±5 V SUPPLY
AD8099
T
A
= 25°C, G = +2, R
L
= 1 kΩ to ground, unless otherwise noted. Refer to Figure 60 through Figure 66 for component values and gain
configurations.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness (SOIC/LFCSP)
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Test Conditions/Comments
G = +5, V
OUT
= 0.2 V p-p
G = +5, V
OUT
= 2 V p-p
G = +2, V
OUT
= 0.2 V p-p
G = +10, V
OUT
= 6 V Step
G = +2, V
OUT
= 2 V Step
G = +2, V
OUT
= 2 V Step
f
C
= 500 kHz, V
OUT
= 2 V p-p, G = +10
f
C
= 10 MHz, V
OUT
= 2 V p-p, G = +10
f = 100 kHz
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +V
S
Min
450
205
1120
435
Typ
510
235
34/25
1350
470
18
−102/−111
−84/−92
0.95
2.6
5.2
0.1
2.3
−6
−0.1
3
0.06
85
4
10
2
−3.7 to +3.7
105
<2.4
105
ns
39
17
35
30/50
−3.6 to +3.7
−3.8 to +3.8
131/178
−61
±5
15
1.7
91
94
±6
16
2
21
44
µA
µA
ns
V
V
mA
dB
V
mA
mA
dB
dB
0.5
−13
−2
1
Max
Unit
MHz
MHz
MHz
V/µs
V/µs
ns
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
mV
µV/°C
µA
µA
nA/°C
µA
dB
kΩ
MΩ
pF
V
dB
V
ns
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
DISABLE Input Voltage
Turn-Off Time
Turn-On Time
Enable Pin Leakage Current
DISABLE Pin Leakage Current
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
DISABLE pin floating
DISABLE pin = +V
S
82
Differential mode
Common mode
V
CM
= ±2.5 V
Output disabled
50% of DISABLE to < 10% of final V
OUT
,
V
IN
= 0.5 V, G = +2
50% of DISABLE to < 10% of final V
OUT
,
V
IN
= 0.5 V, G = +2
DISABLE = +5 V
DISABLE = −5 V
V
IN
= −2.5 V to +2.5 V, G =+2
R
L
= 100 Ω
R
L
= 1 kΩ
Sinking and sourcing
f = 1 MHz, DISABLE = low
98
−3.4 to +3.5
−3.7 to +3.7
DISABLE = Low
+V
S
= 4 V to 6 V, −V
S
= −5 V (input referred)
+V
S
= 5 V, −V
S
= −6 V to −4 V (input referred)
Rev. E | Page 3 of 26
85
86
AD8099
SPECIFICATIONS WITH +5 V SUPPLY
Data Sheet
V
S
= 5 V at T
A
= 25°C, G = +2, R
L
= 1 kΩ to midsupply, unless otherwise noted. Refer to Figure 60 through Figure 66 for component
values and gain configurations.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness (SOIC/LFCSP)
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (dBc) HD2/HD3
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Input Bias Offset Current Drift
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
DISABLE PIN
DISABLE Input Voltage
Turn-Off Time
Turn-On Time
Enable Pin Leakage Current
DISABLE Pin Leakage Current
OUTPUT CHARACTERISTICS
Overdrive Recovery Time (Rise/Fall)
Output Voltage Swing
Short-Circuit Current
Off Isolation
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Disabled)
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Test Conditions/Comments
G = +5, V
OUT
= 0.2 V p-p
G = +5, V
OUT
= 2 V p-p
G = +2, V
OUT
= 0.2 V p-p
G = +10, V
OUT
= 2 V Step
G = +2, V
OUT
= 2 V Step
G = +2, V
OUT
= 2 V Step
f
C
= 500 kHz, V
OUT
= 1 V p-p, G = +10
f
C
= 10 MHz, V
OUT
= 1 V p-p, G = +10
f = 100 kHz
f = 100 kHz, DISABLE pin floating
f = 100 kHz, DISABLE pin = +V
S
Min
415
165
630
340
Typ
440
210
33/23
715
365
18
−82/−94
−80/−75
0.95
2.6
5.2
0.1
2.5
−6.2
−0.2
0.05
2.4
81
4
10
2
1.3 to 3.7
105
<2.4
105
61
16
33
50/70
1.2 to 3.8
1.2 to 3.8
60/80
−61
±5
14.5
1.4
89
90
±6
15.4
1.7
0.5
−13
−2
1
Max
Unit
MHz
MHz
MHz
V/µs
V/µs
ns
dBc
dBc
nV/√Hz
pA/√Hz
pA/√HZ
mV
µV/°C
µA
µA
µA
nA/°C
dB
kΩ
MΩ
pF
V
dB
V
ns
ns
µA
µA
ns
V
V
mA
dB
V
mA
mA
dB
dB
DISABLE pin floating
DISABLE pin = +V
S
V
OUT
= 1 V to 4 V
Differential mode
Common mode
76
V
CM
= 2 V to 3 V
Output disabled
50% of DISABLE to <10% of Final V
OUT
,
V
IN
= 0.5 V, G = +2
50% of DISABLE to <10% of Final V
OUT
,
V
IN
= 0.5 V, G = +2
DISABLE = 5 V
DISABLE = 0 V
V
IN
= 0 to 2.5 V, G = +2
R
L
= 100 Ω
R
L
= 1 kΩ
Sinking and Sourcing
f = 1 MHz, DISABLE = Low
88
21
44
1.5 to 3.5
1.2 to 3.8
DISABLE = Low
+V
S
= 4.5 V to 5.5 V, −V
S
= 0 V (input referred)
+V
S
=5 V, −V
S
= −0.5 V to +0.5 V (input referred)
84
84
Rev. E | Page 4 of 26
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Differential Input Voltage
Differential Input Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12.6 V
See Figure 4
±1.8 V
±10mA
−
65°C to +125°C
−
40°C to +125°C
300°C
150°C
AD8099
V V
P
D
=
(
V
S
×
I
S
)
+
S
×
OUT
R
L
2
V
OUT 2
–
R
L
RMS output voltages should be considered. If R
L
is referenced to
V
S
−, as in single-supply operation, then the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
(
V
S
/
4
)
2
P
D
=
(
V
S
×
I
S
)
+
R
L
In single-supply operation with R
L
referenced to V
S
–, worst case
is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
. Also,
more metal directly in contact with the package leads from metal
traces, through holes, ground, and power planes reduce the θ
JA
.
Soldering the exposed paddle to the ground plane significantly
reduces the overall thermal resistance of the package. Take care
to minimize parasitic capacitances at the input leads of high
speed op amps, as discussed in the PCB Layout section.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EPAD) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on
a JEDEC standard 4-layer board. θ
JA
values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–40
04511-0-115
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the
AD8099
package is
limited by the associated rise in junction temperature (T
J
) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the
AD8099.
Exceeding
a junction temperature of 150°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
the ambient temperature (T
A
), and the total power dissipated in
the package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as
MAXIMUM POWER DISSIPATION (Watts)
LFCSP AND SOIC
T
J
=
T
A
+
(
P
D
×
θ
JA
)
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming the load (R
L
) is referenced to
midsupply, the total drive power is V
S
/2 × I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
=
Quiescent Power
+ (Total
Drive Power
−
Load Power)
–20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
100
120
Figure 4. Maximum Power Dissipation
ESD CAUTION
Rev. E | Page 5 of 26
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