The AS29F010 is a high performance 1 megabit 5 volt-only Flash memory organized as 128K bytes of 8 bits each. It is divided into four
sectors of 32K bytes each. Each sector is separately erased and programmed without affecting data in the other sectors. All prog ram, erase,
and verify operations are 5-volt only, and require no external 12V supply pin. All required features for in-system programmability are
provided.
The AS29F010 provides high performance with a maximum access time of 120, or 150 ns. Chip Enable ( CE), Output Enable (OE), and
Write Enable (WE) pins allow easy interface with the system bus.
Program, erase, and verify operations are controlled with an on-chip command register using a JEDEC standard Write State Machine
approach to enter commands. Each command requires four write cycles to be executed. Address and data are latched internally during all
write, erase, and verify operations, and an internal timer terminates each command. The chip has a typical timer period of 200 µ s for all
commands but Erase, which has a typical period of 800 ms. Under nominal conditions, a sector can be completely programmed and verified
in less than 12 seconds. To program, erase, and verify a sector typically takes less than 18 seconds.
Data protection is provided by a low-V
CC
lockout and by error checking in the Write State Machine. DATA polling and Toggle Bit modes are
used to show that the chip is executing a command when the AS29F010 is read during a write or erase operation. After Erase or P ogram
commands,Verify-1 andVerify-0 command modes ensure sufficient margin for reliable operation. (See command summary on page 5.)
The AS29F010 is packaged in 32-pin DIP, PLCC and TSOP packages with JEDEC standard pinouts for one megabit Flash memories.
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The array consists of 128K (131,072) bytes divided into four sectors of 32K bytes each. Addresses A15 and A16 select the four sectors:
Sector
0
1
2
3
Address range
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
Address pins
A0–A5
A6–A14
A15–A16
Function
CA: Column addresses 00–3Fh
RA: Row addresses 000–1FFh
SA: Sector addresses 0–3h
The AS29F010 is shipped in the erased state with all bits set to 1. Programmed bits are set to 0. Data is programmed into the a ray one byte
at a time. All programmed bits remain set to 0 until the sector is erased and verified using the SectorErase and Verify algorit hm. Erase returns
all bytes in a 32K sector to the erased state FFh, or all bits set to 1. Each sector is erased individually with no effect on the other sectors.
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The AS29F010 is controlled by a Write State Machine (WSM) that interprets and executes commands. At power-up the WSM is reset to
normal read mode. Once a command is initiated by writing data into the DQ pins with the WE pin, the WSM enters the command mode and
keeps the chip powered up until the command is finished. After the command is terminated by the internal timer, the WSM returns to the
normal read mode.
5
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Mode
Read
Output disable
Standby
Mfr. code
Device code
Write command
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Key:
CE
L
L
H
L
L
L
OE
L
H
H
L
L
H
WE
H
H
H
H
H
L
A0
A0
X
X
L
H
A0
A9
A9
X
X
Vh
Vh
A9
DQ
D
OUT
High Z
High Z
52h
CODE (03h,04h,06h)
D
IN
L =Low (<VIL); H = High (>VIH); Vh = 11.5–12.5V; X =Don’t care
Read mode:
Selected with CE and OE low, WE high. Data is valid tAA after addresses are stable, tCE after CE is low and tOE after OE is low.
Output disable:
Part remains powered up; but outputs disabled with OE pulled high.
Standby:
Part is powered down, and ICC reduced to 1.5 mA for TTL input levels (<1.0 mA for CMOS input levels).
Mfr. (manufacturer) code, Device code:
Selected by A9 = 11.5–12.5V. When CE and OE are pulled low the outputs are enabled and a data byte is read out.
When A0 is pulled low the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high DOUT = 03h,04h, 06h, the
Alliance device codes for the AS29F010.
Write command:
Selected by CE and WE pulled low, OE pulled high. Initiates command mode in the WSM and latches addresses and data into the chip. Once
a write command starts, the WSM stays in command mode until the command is completed or it times out. Addresses are latched on the falling edge of WE
and CE, whichever occurs later; data is latched on the rising edge o WE and CE, whichever occurs first. The WE signal is filtered to prevent spurious events
from being detected as write commands.
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All commands require four bus write cycles to execute. After four write cycles the command is executed until terminated by the i nternal
timer. For verify commands a read operation after Write
[4]
in a write command bus cycle reads out the data from thearray. For manufacturer
and device code commands the ID code is read out. For other operations a read operation reads out a status byte on the outputs.
Address in
Bus write
[1]
Bus write
[2]
Bus write
[3]
Bus write
[4]
Bus read
5555h
2AAAh
5555h
Address in
Address in
Data in
AAh
55h
Command code
Data in
D
OUT
Command timeout:
For each operation the address and data are latched at
bus Write
[4]
and held until the operation completes and times-out. After
time-out the WSM returns the AS29F010 to normal mode. Each individual
operation requires the 4-cycle write command sequence to execute. The
AS29F010 does not remain in command mode after time-out. When a
command times-out only the error flag is not reset.
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Errors a
nd timeout:
Any of the following conditions sets the error flag.
• Any write command which does not match the sequence above for Write
{1]
. Write
{2]
, and Write
[3]
.
• Any write cycle that follows more than 150 µs after the previous write cycle.
• The command Data
[3]
in Write
[3]
has more than one bit set high. This indicates conflicting commands.
• V
CC
drops below V
LKO
during command execution.
Once the error flag is set, the AS29F010 times out and returns to normal Readmode. The error flag remains until it is cleared by a reset
command. The error flag can be read by executing a status command and reading the status byte.
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The Command Code table displays the bus cycles required for each command mode. Read delay is the minimum delay after Write
[4]
during
a write command bus cycle before a valid read may be executed. Timeout indicates the maximum delay before the WSM returns the
AS29F010 to normal mode. Erase has a longer timeout than the other modes. Status byte can be read almost immediately after a Write
[4]
, but
the verify commands require a 25 µs delay to read valid data.
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Mode
Reset
Status
ID Read
code
Verify-0
Verify-1
Converge
Program
Erase
D
IN[3]
Write
[3]
data
00h
01h
02h
04h
08h
10h
40h
80h
A
IN[4]
Write
[4]
address
x
x
0000h
0001h
A
IN
A
IN
A
IN
A
IN
A
IN
D
IN[4]
data
x
x
x
x
x
x
00h
D
IN
FFh
Read address
0000h
0000h
0000h
0001h
A
IN
A
IN
A
IN
A
IN
A
IN
Read data
Status
Status
Mfr. code
Device code
D
OUT
D
OUT
Status
Status
Status
Read delay
100 ns
100 ns
52h 100 ns
04h 100 ns
25 µs
25 µs
100 ns
100 ns
100 ns
Maximum time out
250 µs
250 µs
250 µs
250 µs
250 µs
250 µs
250 µs
1000 µs
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Individual write commands are used together in eight program and erase algorithms to guarantee the AS29F010 operating margins for the
life of the part. Refer to the AS29F010 Programming Specification for details on the algorithms for program and erase operation .
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Parameter
Supply voltage
Input voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.0
–0.5
Typ
5.0
0
-
-
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Max
5.5
0
V
CC
+ 1.0
0.8
Unit
V
V
V
V
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Parameter
Input voltage (Input or DQ pin)
Input voltage (A9 pin)
Output voltage
Power supply voltage
Operating temperature
Storage temperature (plastic)
Short circuit output current
Latch-up current
Symbol
V
IN
V
IN
V
OUT
V
CC
T
OPR
T
STG
I
OUT
I
IN
Min
–1.0
–1.0
–1.0
+4.5
–55
–65
-
-
Max
V
CC
+ 1.0
+13.0
V
CC
+ 1.0
+5.5
+125
+125
100
±100
Unit
V
V
V
V
°C
°C
mA
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
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20 ns
20 ns
-2.0V
V
CC
+2.0V
V
CC
+0.5V
+2.0V
20 ns
20 ns
20 ns
+0.8V
-0.5V
20 ns
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Parameter
Input load current
Output leakage current
Output short circuit current
Active current, read @ 6MHz
Active current, program/erase
Standby current
Input: low level
Input: high level
Output low voltage
Output high level
Low V
CC
lock out voltage
Input HV select voltage
Symbol
I
LI
I
LO
I
OS
I
CC
I
CCPRG
I
SB1
(TTL)
I
CCPD
V
IL
V
IH
V
OL
V
OH1
V
OH2
V
LKO
V
ID
I
OL
= 12mA
I
OH
= -2.5 mA
I
OH
= -100 µA
Test conditions
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Min
-
-
-
-
-
-
-
-
0.5
2.0
-
2.4
V
CC
- 0.4
3.2
11.5
Max
±1
±1
100
30
50
1.5
1.0
2
0.8
V
SS
+ 0.3
0.45
-
-
4.2
12.5
Unit
µA
µA
mA
mA
mA
mA
mA
µA
V
V
V
IN
= V
SS
to V
CC
, V
SS
= V
MAX
V
OUT
= V
SS
to V
CC
, V
SS
= V
MAX
V
OUT
= 0.5V
CE = V
IL
, OE = V
IH
CE = V
IL
, OE = V
IH
CE = V
IH
RP = 0V
I
SB2
(CMOS) CE = V
CC
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V
V
V
V
V
1RWHV
1
2
3
Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second.
OUT
= 0.5V was selected to avoid test problems
caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.)
The I
CC
current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency component typically
is less than 2 mA/MHz with OE at V
IH
.
I
CC
active while program or erase operations are in progress.
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