DATASHEET
ISL59885
Auto-Adjusting Sync Separator for HD and SD Video
The ISL59885 video sync separator extracts sync timing
information from both standard and non-standard video inputs
in the presence of Macrovision pulses. The ISL59885 provides
horizontal, vertical, and composite sync outputs as well as
SD/HDTV detection. An auto input frequency detect feature
automatically adapts to a wide range of video standards (it
does not need a different RSET resistor for different
frequencies). The vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
low for longer than the vertical sync default delay time. The
horizontal output gives horizontal timing with pre/post
equalizing pulses. Fixed 70mV sync tip slicing provides sync
edge detection when the video input level is between 0.5V
P-P
and 2V
P-P
.
The ISL59885 is available in an 8 Ld SOIC package and is
specified for operation over the full -40°C to +85°C
temperature range.
FN7442
Rev 8.00
October 31, 2011
Features
• NTSC, PAL, SECAM, HDTV, Non-standard Video Sync
Separation
• Fixed 70mV Slicing of Video Input Levels from 0.5V
P-P
to
2V
P-P
• Single 3V to 5V Supply
• Composite Sync Output
• Vertical Output
• Horizontal Output
• HDTV Detection
• Macrovision Compatible
• Available in 8 Ld SOIC Package
• Pb-free (RoHS Compliant)
Applications
• High-definition Video Equipment
Related Literature
•
AN1269,
“One Transistor Enables Clean HDTV and NTSC
Video Sync Separation”
•
AN1316,
“One Transistor Enables Clean HDTV and NTSC
Video Sync Separation”
•
TB476,
“Regenerating H
SYNC
from Corrupted SOG or C
SYNC
during V
SYNC
”
CLAMP
SYNC TIP REF
1.5V
COMPOSITE
VIDEO IN
2
SLICE
1.57V
GND 4
C
SET
C
3
56nF
SYNC
TIP
70mV
SLICE
HD
DETECTOR
5 HD
V
DD
8
V
DD
5V
C
2
0.1µF
COMP.
-
+
1 COMPOSITE
SYNC
R
F
620Ω
C
F
510pF
C
1
0.1µF
6
REF
GEN
V SYNC
3 VERTICAL
SYNC OUT
H SYNC
7 HORIZONTAL
SYNC OUT
2H
ELIMINATOR
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM
FN7442 Rev 8.00
October 31, 2011
Page 1 of 15
ISL59885
Pin Configuration
ISL59885
(8 LD SOIC)
TOP VIEW
COMPOSITE SYNC OUT 1
COMPOSITE VIDEO IN 2
VERTICAL SYNC OUT 3
GND 4
8 VDD
7 HORIZONTAL OUTPUT
6 CSET
5 HD
Pin Descriptions
PIN
NUMBER
1
PIN NAME
Composite
Sync Out
Composite
Video In
Vertical
Sync Out
GND
HD
CSET
Horizontal
Output
VDD
PIN FUNCTION
Composite sync pulse output; sync pulses
start on a falling edge and end on a rising
edge.
AC-coupled composite video input; sync tip
must be at the lowest potential (positive
picture phase).
Vertical sync pulse output; the falling edge
of vertical sync is the start of the vertical
period.
Supply ground
Low when input horizontal frequency is
greater than 25kHz.
(An external capacitor to ground); bypass
pin for internal bias generator.
Horizontal output; falling edge active
Positive supply
2
3
4
5
6
7
8
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL59885ISZ
ISL59885ISZ-EVAL
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL59885.
For more information on MSL, please see Tech Brief
TB363.
PART MARKING
59885 ISZ
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG. DWG. #
M8.15E
FN7442 Rev 8.00
October 31, 2011
Page 2 of 15
ISL59885
Absolute Maximum Ratings
(T
A
= +25
°
C)
V
DD
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V
CC
+0.5V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld SOIC Package (Notes 4, 5) . . . . . . . . .
120
66
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Ambient Temperature Range . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. For
JC
, the “case temp” location is taken at the package top center.
DC Electrical Specifications
operating temperature range, -40°C to +85°C.
PARAMETER
I
DD
, Quiescent
Clamp Voltage
Clamp Discharge Current
Clamp Charge Current
V
OL
Output Low Voltage
V
OH
Output High Voltage
V
DD
= 3.3V, T
A
= +25°C, C
SET
= 56nF, unless otherwise specified.
Boldface limits apply over the
MIN
(Note 6)
1
1.35
6
-9
MAX
(Note 6)
4
1.65
30
-5.2
0.5
DESCRIPTION
V
DD
= 3.3V
Pin 2, I
LOAD
= -100µA
Pin 2 = 2V
Pin 2 = 1V
I
OL
= 1.6mA
I
OH
= -40µA
I
OH
= -1.6mA
TYP
2.2
1.5
15
-7.2
0.24
UNIT
mA
V
µA
mA
V
V
V
3
2.5
3.2
3.0
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Dynamic Characteristics
PARAMETER
Comp Sync Prop Delay, t
CS
Horizontal Sync Delay, t
HS
Horizontal Sync Width, t
HS-PW
Vertical Sync Width, t
VS
Vertical Sync Default Delay, t
VSD
Hsync Blanking Window
Input Dynamic Range
Slice Level
HD Pin Level
Boldface limits apply over the operating temperature range, -40°C to +85°C.
DESCRIPTION
(See Figure 8)
(See Figure 8)
(See Figure 8)
Normal or default trigger, 50% to 50%
(see Figure 7)
(See Figure 9)
3.8
230
28
70
Video input amplitude to maintain slice level
spec, V
DD
= 3.3V
V
SLICE
above V
CLAMP
720p, 1080i, 1080p
0.5
50
70
0
MIN
(Note 6)
TYP
35
40
5.2
280
50
80
MAX
(Note 6)
75
80
6.2
350
68
90
2
90
UNIT
ns
ns
µs
µs
µs
%
V
P-P
mV
V
FN7442 Rev 8.00
October 31, 2011
Page 3 of 15
ISL59885
Typical Performance Curves
V
DD
= 3.3 AND 5.0V
H
SYNC
PULSE WIDTH (ns)
V
DD
= 3.3 AND 5.0V
V
CSET
(V)
k
k
k
k
k
H
SYNC
(Hz)
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
H
SYNC
FREQUENCY (Hz)
FIGURE 2. H
SYNC
vs V
CSET
(R
SET
= OPEN)
FIGURE 3. H
SYNC
PULSE WIDTH vs H
SYNC
FREQUENCY
(R
SET
= OPEN)
V
DD
= 3.3 AND 5.0V
H
SYNC
BLANKING TIME (µs)
0.5V/DIV
5V/DIV
5V/DIV
VIN
HSYNC
VSYNC
5V/DIV
CSYNC
100µs/DIV
V
CSET
(V)
FIGURE 4. H
SYNC
vs V
CSET
(R
SET
= OPEN)
FIGURE 5. MACROVISION COMPATIBILITY (NTSC)
1.2
MAX POWER DISSIPATION (W)
1.0
0.8
0.6
0.4
0.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
8 PIN SOIC PACKAGE
JA
= 120°C/W
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
AMBIENT TEMPERATURE (°C)
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7442 Rev 8.00
October 31, 2011
Page 4 of 15
ISL59885
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5µs ±0.1µs
TIME
VERTICAL BLANKING INTERVAL = 20H
3H
3
4
5
6
7
3H
8
+63.5µs
+H
1271µs
-0µs
-H
3H
1
2
9
10
19
20
21
H SYNC
INTERVAL
H
START OF
H
FIELD ONE
PRE-
EQUALIZING
PULSE INTERVAL
H
VERTICAL SYNC
PULSE INTERVAL
9 LINE VERTICAL INTERVAL
0.5H
POST-
EQUALIZING
PULSE INTERVAL
H
REF SUBCARRIER PHASE,
COLOR FIELD ONE
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
t
VS
SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES:
7. The composite sync output reproduces all the video input sync pulses, with a propagation delay.
8. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
9. Horizontal sync output produces the “H” pulses of nominal width of 5µs. It has the same delay as the composite sync.
FIGURE 7. TIMING DIAGRAM
FN7442 Rev 8.00
October 31, 2011
Page 5 of 15
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