DS1743/DS1743P
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
Integrated NV SRAM, real time clock, crystal, power-
fail control circuit and lithium energy source
Clock registers are accessed identical to the static
RAM. These registers are resident in the eight top
RAM locations.
Century byte register
Totally nonvolatile with over 10 years of operation in
the absence of power
BCD coded century, year, month, date, day, hours,
minutes, and seconds with automatic leap year
compensation valid up to the year 2100
Battery voltage level indicator flag
Power-fail write protection allows for
±10%
V
CC
power supply tolerance
Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
DIP Module only
–
Standard JEDEC bytewide 8k x 8 static RAM
pinout
PowerCap
Module Board only
–
Surface mountable package for direct connection
to PowerCap containing battery and crystal
–
Replaceable battery (PowerCap)
–
Power-On Reset Output
–
Pin for pin compatible with other densities of
DS174XP Timekeeping RAM
PIN ASSIGNMENT
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28-Pin Encapsulated Package
(700-mil Extended)
NC
NC
NC
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
NC
NC
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
X1
GND V
BAT
X2
ORDERING INFORMATION
DS1743P-XXX (5V)
-70
-100
blank
P
70 ns access
100 ns access
34-Pin Powercap Module Board
(Uses DS9034PCX Powercap)
PIN DESCRIPTION
A0-A12
CE
28-pin DIP Module
34-pin PowerCap Module
board*
(3.3V)
-120
120 ns access
-150
150 ns access
CE2
OE
WE
*DS1743WP-XXX
28-pin DIP Module
34-pin PowerCap Module
board*
*DS9034PCX (PowerCap) Required:
blank
P
V
CC
GND
DQ0-DQ7
NC
RST
(must be ordered separately)
X1, X2
V
BAT
1 of 17
- Address Input
- Chip Enable
- Chip Enable 2 (DIP
Module only)
- Output Enable
- Write Enable
- Power Supply Input
- Ground
- Data Input/Output
- No Connection
- Power-On Reset Output
(PowerCap Module board only)
- Crystal Connection
- Battery Connection
022301
DS1743/DS1743P
DESCRIPTION
The DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
non-volatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the
eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are
made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that
can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its
own power-fail circuitry, which deselects the device when the V
CC
supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1743 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All of the DS1743 registers are updated simultaneously after the internal clock
register updating process has been re-enabled. Updating is within a second after the read bit is written to
0.
The READ bit must be a zero for a minimum of 500
µs
to ensure the external registers will be updated.
2 of 17
DS1743/DS1743P
DS1743 BLOCK DIAGRAM
Figure 1
DS1743 TRUTH TABLE
Table 1
V
CC
V
CC
>V
PF
CE
V
SO
<V
CC
<V
PF
V
CC
<V
SO
<V
PF
V
IH
X
V
IL
V
IL
V
IL
X
X
CE2
X
V
IL
V
IH
V
IH
V
IH
X
X
OE
WE
X
X
X
V
IL
V
IH
X
X
X
X
V
IL
V
IH
V
IH
X
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for seconds register remain valid and
stable).
3 of 17
DS1743/DS1743P
The DS1743 is guaranteed to keep time accuracy to within
±1
minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
CLOCK ACCURACY (DIP MODULE)
CLOCK ACCURACY (POWERCAP MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within
±1.53
minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1743 REGISTER MAP
Table 2
ADDRESS
DATA
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION/RANGE
1FFF
1FFE
1FFD
1FFC
1FFB
1FFA
1FF9
1FF8
OSC
X
X
BF
X
X
OSC
W
R
X
X
10 Year
X
X
10 MINUTES
10 SECONDS
10 CENTURY
10 Mo
10 Date
X
X
10 HOUR
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CONTROL
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
FT
X
= STOP BIT
W = WRITE BIT
R = READ BIT
X = SEE NOTE BELOW
FT = FREQUENCY TEST
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever
OE
(output enable) is low,
WE
(write enable) is high, and
CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
AA
after the last address input is
stable, providing that the
CE
, and
OE
access times and states are satisfied. If
CE
, or
OE
access times and
states are not met, valid data will be available at the latter of chip enable access (t
CEA
) or at output enable
access time (t
CEA
). The state of the data input/output pins (DQ) is controlled by
CE
, and
OE
. If the
outputs are activated before t
AA
, the data lines are driven to an intermediate state until t
AA
. If the address
inputs are changed while
CE
, and
OE
remain valid, output data will remain valid for output data hold time
(t
OH
) but will then go indeterminate until the next address access.
4 of 17
DS1743/DS1743P
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever
WE
, and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
, on
CE
. The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on
WE
will
then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when V
CC
is greater than V
PF.
However, when V
CC
is below the power fail point, V
PF
,
(point at which write protection occurs) the internal
clock registers and SRAM are blocked from any access. At this time(PowerCap only)the power fail reset
output signal (
RST ) is driven active and will remain active until V
CC
returns to nominal levels. When V
CC
falls below the battery switch point V
SO
(battery supply level), device power is switched from the V
CC
pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels. The 3.3-volt device is fully accessible and data can be written or read only when V
CC
is
greater than V
PF.
When V
CC
falls below the power fail point, V
PF
,
access to the device is inhibited. At this
time the power fail reset output signal ( RST ) is driven active and will remain active until V
CC
returns to
nominal levels. If V
PF
is less than Vso
,
the device power is switched from V
CC
to the backup supply (V
BAT
)
when V
CC
drops below V
PF.
If V
PF
is greater than Vso, the device power is switched from V
CC
to the backup
supply (V
BAT)
when V
CC
drops below Vso. RTC operation and SRAM data are maintained from the battery
until V
CC
is returned to nominal levels. The RST (PowerCap only) signal is an open drain output and
requires a pull up. Except for the RST , all control, data, and address signals must be powered down when
V
CC
is powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the V
CC
supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25
°
C with the internal clock oscillator running in
the absence of V
CC
power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than
V
PF
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be much longer than 10 years since no lithium battery energy is consumed when V
CC
is
present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC and RAM are questionable.
5 of 17
京公网安备 11010802033920号
EEWORLD
