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74CBTLV16211
24-bit bus switch
Rev. 7 — 9 November 2016
Product data sheet
1. General description
The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output
enable inputs (1OE, 2OE). The low on-state resistance of the switch allows connections to
be made with minimal propagation delay. The switch is disabled (high-impedance
OFF-state) when the output enable (nOE) input is HIGH.
To ensure the high-impedance OFF-state during power-up or power-down, 1OE and 2OE
should be tied to the V
CC
through a pull-up resistor. The minimum value of the resistor is
determined by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 2.3 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5
switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
OFF
circuitry provides partial Power-down mode operation
TSSOP56 packages: SOT364-1 and SOT481-2
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74CBTLV16211
24-bit bus switch
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74CBTLV16211DGG
74CBTLV16211DGV
40 C
to +125
C
40 C
to +125
C
Name
Description
Version
SOT364-1
SOT481-2
Type number
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 4.4 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one switch)
74CBTLV16211
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 9 November 2016
2 of 17
NXP Semiconductors
74CBTLV16211
24-bit bus switch
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration (SOT364-1 and SOT481-2)
5.2 Pin description
Table 2.
Symbol
n.c.
1A0 to 1A11
2A0 to 2A11
GND
V
CC
2B0 to 2B11
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14
15, 16, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28
8, 19, 38, 49
17
41, 40, 39, 37, 36, 35, 34, 33, 32, 31, 30, 29
Description
not connected
independent input or output
independent input or output
ground (0 V)
supply voltage
independent input or output
74CBTLV16211
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 9 November 2016
3 of 17
NXP Semiconductors
74CBTLV16211
24-bit bus switch
Table 2.
Symbol
Pin description
…continued
Pin
54, 53, 52, 51, 50, 48, 47, 46, 45, 44, 43, 42
55
56
Description
independent input or output
output enable input (active-LOW)
output enable input (active-LOW)
1B0 to 1B11
2OE
1OE
6. Functional description
Table 3.
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Function switch
ON-state
OFF-state
Output enable input OE
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
50
50
-
-
100
65
Max
+4.6
+4.6
V
CC
+ 0.5
-
-
128
+100
-
+150
600
Unit
V
V
V
mA
mA
mA
mA
mA
C
mW
enable and disable mode
V
I
<
0.5
V
V
I
<
0.5
V
V
SW
= 0 V to V
CC
[1]
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP56 packages: above 55
C
the value of P
tot
derates linearly with 8.0 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
SW
T
amb
t/V
[1]
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.3 V to 3.6 V
[1]
Conditions
Min
2.3
0
Max
3.6
3.6
V
CC
+125
200
Unit
V
V
V
C
ns/V
enable and disable mode
0
40
0
Applies to control signal levels.
74CBTLV16211
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 9 November 2016
4 of 17
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