DS26528
Octal T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
FEATURES
Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26528
T1/E1/J1
NETWORK
T1/J1/E1
Transceiver
x8
BACKPLANE
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
TDM
ORDERING INFORMATION
PART
DS26528G
DS26528G+
DS26528GN
DS26528GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section
2.
+ Denotes lead-free/RoHS compliant device.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 112907
DS26528 Octal T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
1.1
DETAILED DESCRIPTION.................................................................................................9
M
AJOR
O
PERATING
M
ODES
.............................................................................................................9
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
FEATURE HIGHLIGHTS ..................................................................................................10
G
ENERAL
......................................................................................................................................10
L
INE
I
NTERFACE
............................................................................................................................10
C
LOCK
S
YNTHESIZER
....................................................................................................................10
J
ITTER
A
TTENUATOR
.....................................................................................................................10
F
RAMER
/F
ORMATTER
....................................................................................................................10
S
YSTEM
I
NTERFACE
......................................................................................................................11
HDLC C
ONTROLLERS
...................................................................................................................12
T
EST AND
D
IAGNOSTICS
................................................................................................................12
C
ONTROL
P
ORT
............................................................................................................................12
3.
4.
5.
6.
7.
7.1
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
BLOCK DIAGRAMS.........................................................................................................17
PIN DESCRIPTIONS ........................................................................................................19
P
IN
F
UNCTIONAL
D
ESCRIPTION
......................................................................................................19
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
FUNCTIONAL DESCRIPTION .........................................................................................27
P
ROCESSOR
I
NTERFACE
................................................................................................................27
C
LOCK
S
TRUCTURE
.......................................................................................................................27
Backplane Clock Generation ............................................................................................................... 27
8.2.1
R
ESETS AND
P
OWER
-D
OWN
M
ODES
..............................................................................................29
I
NITIALIZATION AND
C
ONFIGURATION
..............................................................................................30
Example Device Initialization Sequence .............................................................................................. 30
8.4.1
G
LOBAL
R
ESOURCES
....................................................................................................................30
P
ER
-P
ORT
R
ESOURCES
................................................................................................................30
D
EVICE
I
NTERRUPTS
.....................................................................................................................30
S
YSTEM
B
ACKPLANE
I
NTERFACE
...................................................................................................32
Elastic Stores ....................................................................................................................................... 32
IBO Multiplexer..................................................................................................................................... 35
H.100 (CT Bus) Compatibility .............................................................................................................. 42
Receive and Transmit Channel Blocking Registers............................................................................. 43
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 43
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 43
T1 Framing........................................................................................................................................... 44
E1 Framing........................................................................................................................................... 47
T1 Transmit Synchronizer .................................................................................................................... 49
Signaling .............................................................................................................................................. 50
T1 Data Link......................................................................................................................................... 54
E1 Data Link......................................................................................................................................... 56
Maintenance and Alarms ..................................................................................................................... 57
E1 Automatic Alarm Generation .......................................................................................................... 60
Error-Count Registers .......................................................................................................................... 61
DS0 Monitoring Function...................................................................................................................... 63
Transmit Per-Channel Idle Code Insertion........................................................................................... 64
2 of 276
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
F
RAMERS
......................................................................................................................................44
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
DS26528 Octal T1/E1/J1 Transceiver
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
Receive Per-Channel Idle Code Insertion............................................................................................ 64
Per-Channel Loopback ........................................................................................................................ 64
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 64
T1 Programmable In-Band Loop Code Generator............................................................................... 65
T1 Programmable In-Band Loop Code Detection................................................................................ 66
Framer Payload Loopbacks ................................................................................................................. 67
8.10
8.10.1
8.10.2
HDLC C
ONTROLLERS
................................................................................................................68
Receive HDLC Controller..................................................................................................................... 68
Transmit HDLC Controller.................................................................................................................... 71
8.11
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
L
INE
I
NTERFACE
U
NITS
(LIU
S
)....................................................................................................73
LIU Operation....................................................................................................................................... 76
Transmitter ........................................................................................................................................... 77
Receiver ............................................................................................................................................... 80
Jitter Attenuator.................................................................................................................................... 83
LIU Loopbacks ..................................................................................................................................... 84
8.12
8.12.1
8.12.2
B
IT
-E
RROR
-R
ATE
T
EST
(BERT) F
UNCTION
................................................................................86
BERT Repetitive Pattern Set ............................................................................................................... 87
BERT Error Counter............................................................................................................................. 87
9.
9.1
DEVICE REGISTERS .......................................................................................................88
R
EGISTER
L
ISTINGS
......................................................................................................................88
Global Register List.............................................................................................................................. 90
Framer Register List............................................................................................................................. 91
LIU and BERT Register List................................................................................................................. 98
Global Register Bit Map ....................................................................................................................... 99
Framer Register Bit Map .................................................................................................................... 100
LIU Register Bit Map .......................................................................................................................... 108
BERT Register Bit Map ...................................................................................................................... 108
9.1.1
9.1.2
9.1.3
9.2
R
EGISTER
B
IT
M
APS
......................................................................................................................99
9.2.1
9.2.2
9.2.3
9.2.4
9.3
9.4
9.5
9.6
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................109
F
RAMER
R
EGISTER
D
EFINITIONS
.................................................................................................124
Receive Register Definitions.............................................................................................................. 124
Transmit Register Definitions............................................................................................................. 183
9.4.1
9.4.2
LIU R
EGISTER
D
EFINITIONS
.........................................................................................................218
BERT R
EGISTER
D
EFINITIONS
.....................................................................................................227
10.
FUNCTIONAL TIMING ...................................................................................................235
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................235
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................240
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
..........................................................................245
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................247
T
HERMAL
C
HARACTERISTICS
....................................................................................................251
L
INE
I
NTERFACE
C
HARACTERISTICS
..........................................................................................251
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
........................................................................252
JTAG I
NTERFACE
T
IMING
.........................................................................................................261
S
YSTEM
C
LOCK
AC C
HARACTERISTICS
....................................................................................262
TAP C
ONTROLLER
S
TATE
M
ACHINE
.........................................................................................264
Test-Logic-Reset................................................................................................................................ 264
Run-Test-Idle ..................................................................................................................................... 264
Select-DR-Scan ................................................................................................................................. 264
Capture-DR ........................................................................................................................................ 264
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10.1
10.2
10.3
10.4
11.
OPERATING PARAMETERS.........................................................................................250
11.1
11.2
12.
AC TIMING CHARACTERISTICS ..................................................................................252
12.1
12.2
12.3
13.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................263
13.1.1
13.1.2
13.1.3
13.1.4
13.1
DS26528 Octal T1/E1/J1 Transceiver
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.1.10
13.1.11
13.1.12
13.1.13
13.1.14
13.1.15
13.1.16
Shift-DR.............................................................................................................................................. 264
Exit1-DR............................................................................................................................................. 264
Pause-DR........................................................................................................................................... 264
Exit2-DR............................................................................................................................................. 264
Update-DR ......................................................................................................................................... 264
Select-IR-Scan ............................................................................................................................... 264
Capture-IR ...................................................................................................................................... 265
Shift-IR............................................................................................................................................ 265
Exit1-IR........................................................................................................................................... 265
Pause-IR......................................................................................................................................... 265
Exit2-IR........................................................................................................................................... 265
Update-IR ....................................................................................................................................... 265
SAMPLE:PRELOAD .......................................................................................................................... 267
BYPASS ............................................................................................................................................. 267
EXTEST ............................................................................................................................................. 267
CLAMP............................................................................................................................................... 267
HIGHZ ................................................................................................................................................ 267
IDCODE ............................................................................................................................................. 267
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
I
NSTRUCTION
R
EGISTER
...........................................................................................................267
13.3
13.4
13.4.1
13.4.2
13.4.3
JTAG ID C
ODES
......................................................................................................................268
T
EST
R
EGISTERS
.....................................................................................................................268
Boundary Scan Register .................................................................................................................... 268
Bypass Register ................................................................................................................................. 268
Identification Register......................................................................................................................... 268
14.
15.
16.
PIN CONFIGURATION...................................................................................................273
PACKAGE INFORMATION ............................................................................................274
256-B
ALL
TE-CSBGA (56-G6028-001) ...................................................................................274
15.1
DOCUMENT REVISION HISTORY ................................................................................275
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DS26528 Octal T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 28
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 31
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 36
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 37
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 38
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 42
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 43
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 64
Figure 8-9. Receive HDLC Example.......................................................................................................................... 70
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 72
Figure 8-11. Basic Balanced Network Connections .................................................................................................. 74
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 78
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 79
Figure 8-14. Typical Monitor Application ................................................................................................................... 81
Figure 8-15. Jitter Attenuation ................................................................................................................................... 83
Figure 8-16. Analog Loopback................................................................................................................................... 84
Figure 8-17. Local Loopback ..................................................................................................................................... 84
Figure 8-18. Remote Loopback ................................................................................................................................. 85
Figure 8-19. Dual Loopback ...................................................................................................................................... 85
Figure 9-1. Register Memory Map for the DS26528.................................................................................................. 89
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 235
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 235
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 236
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 236
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 237
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 238
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 239
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 240
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 240
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 241
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 241
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 242
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 243
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 244
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 245
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 245
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 246
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 246
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 247
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 247
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 248
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 248
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 249
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 253
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 253
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 254
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Analogue and Mixed Signal
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