MC14551B
Quad 2-Channel Analog
Multiplexer/Demultiplexer
The MC14551B is a digitally−controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.
Features
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•
Triple Diode Protection on All Control Inputs
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Analog Voltage Range (V
DD
− V
EE
) = 3.0 to 18 V
•
•
•
•
•
•
1
SOIC−16
D SUFFIX
CASE 751B
Note: V
EE
must be
≤
V
SS
Linearized Transfer Characteristics
Low Noise − 12 nV√Cycle, f
≥
1.0 kHz typical
For Low R
ON
, Use The HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
Switch Function is Break Before Make
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
PIN ASSIGNMENT
W1
X0
X1
X
Y
Y0
V
EE
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
W0
W
Z
Z1
Z0
Y1
CONTROL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Parameter
Symbol
V
DD
Value
Unit
V
V
DC Supply Voltage Range
(Referenced to V
EE
, V
SS
≥
V
EE
)
– 0.5 to + 18.0
– 0.5 to V
DD
+ 0.5
±10
±25
500
– 55 to + 125
– 65 to + 150
260
Input or Output Voltage (DC or Transient)
(Referenced to V
SS
for Control Input and
V
EE
for Switch I/O)
Input Current (DC or Transient),
per Control Pin
Switch Through Current
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8–Second Soldering)
V
in
, V
out
I
in
I
sw
P
D
T
A
T
stg
T
L
mA
mA
mW
_C
_C
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: −7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
for control inputs and V
EE
≤
(V
in
or V
out
)
≤
V
DD
for Switch I/O.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2014
MARKING DIAGRAM
16
14551BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
July, 2014 − Rev. 9
Publication Order Number:
MC14551B/D
MC14551B
ELECTRICAL CHARACTERISTICS
– 55_C
Characteristic
V
DD
−
5.0
10
15
Test Conditions
V
DD
– 3.0
≥
V
SS
≥
V
EE
Control Inputs: V
in =
V
SS
or V
DD
,
Switch I/O: V
EE
v
V
I/O
v
V
DD
, and
DV
switch
v
500 mV (Note 3 )
T
A
= 25_C only (The
channel component,
(V
in
– V
out
)/R
on
, is
not included.)
Symbol
Min
Max
Min
25_C
Typ
(Note 2)
Max
125_C
Min
Max
Unit
SUPPLY REQUIREMENTS
(Voltages Referenced to V
EE
)
Power Supply Voltage
Range
Quiescent Current Per
Package
V
DD
I
DD
3.0
−
−
−
18
5.0
10
20
3.0
−
−
−
−
0.005
0.010
0.015
18
5.0
10
20
3.0
−
−
−
18
150
300
600
V
mA
Total Supply Current
(Dynamic Plus Quiescent,
Per Package)
5.0
10
15
I
D(AV)
Typical
(0.07
mA/kHz)
f + I
DD
(0.20
mA/kHz)
f + I
DD
(0.36
mA/kHz)
f + I
DD
mA
CONTROL INPUT
(Voltages Referenced to V
SS
)
Low−Level Input Voltage
5.0
10
15
5.0
10
15
15
−
R
on
= per spec,
I
off
= per spec
R
on
= per spec,
I
off
= per spec
V
in
= 0 or V
DD
V
IL
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
±0.1
−
−
−
−
3.5
7.0
11
−
−
2.25
4.50
6.75
2.75
5.50
8.25
±0.00001
5.0
1.5
3.0
4.0
−
−
−
±0.1
7.5
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
±1.0
−
V
High−Level Input Voltage
V
IH
V
Input Leakage Current
Input Capacitance
I
in
C
in
mA
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z
(Voltages Referenced to V
EE
)
Recommended Peak−to−
Peak Voltage Into or Out
of the Switch
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 3)
Output Offset Voltage
ON Resistance
−
Channel On or Off
V
I/O
0
V
DD
0
−
V
DD
0
V
DD
V
p–p
−
Channel On
DV
switch
0
600
0
−
600
0
300
mV
−
5.0
10
15
V
in
= 0 V, No Load
DV
switch
v
500 mV
(Note 3),
V
in
= V
IL
or V
IH
(Control), and V
in
= 0 to
V
DD
(Switch)
V
OO
R
on
−
−
−
−
800
400
220
−
−
−
−
10
250
120
80
−
1050
500
280
−
−
−
−
−
1200
520
300
mV
W
DON
Resistance Between
Any Two Channels
in the Same Package
Off−Channel Leakage
Current (Figure 8)
5.0
10
15
15
V
in
= V
IL
or V
IH
(Control) Channel to
Channel or Any One
Channel
Switch Off
DR
on
−
−
−
−
70
50
45
±100
−
−
−
−
25
10
10
±0.05
70
50
45
±100
−
−
−
−
135
95
65
±1000
W
I
off
nA
Capacitance, Switch I/O
Capacitance, Common O/I
Capacitance, Feedthrough
(Channel Off)
−
−
−
−
C
I/O
C
O/I
−
−
−
−
−
−
−
−
−
−
−
−
10
17
0.15
0.47
−
−
−
−
−
−
−
−
−
−
−
−
pF
pF
pF
Pins Not Adjacent
Pins Adjacent
C
I/O
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV
switch
) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may be drawn; i.e. the
current out of the switch may contain both V
DD
and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
MC14551B
ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, T
A
= 25_C, V
EE
v
V
SS
)
Characteristic
Propagation Delay Times
Switch Input to Switch Output (R
L
= 10 kW)
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 26.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 11 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 9.0 ns
Control Input to Output (R
L
= 10 kW)
V
EE
= V
SS
(Figure 4)
Symbol
t
PLH
, t
PHL
5.0
10
15
t
PLH
, t
PHL
5.0
10
15
−
BW
10
10
−
−
−
350
140
100
0.07
17
875
350
250
−
−
%
MHz
V
DD
– V
EE
Vdc
Min
−
35
15
12
90
40
30
ns
Typ
(Note 4 )
Max
Unit
ns
Second Harmonic Distortion
R
L
= 10 kW, f = 1 kHz, V
in
= 5 V
p−p
Bandwidth (Figure 5)
R
L
= 1 kW, V
in
= 1/2 (V
DD
− V
EE
)
p−p
,
20 Log (V
out
/ V
in
) = − 3 dB, C
L
= 50 pF
Off Channel Feedthrough Attenuation, Figure 5
R
L
= 1 kW, V
in
= 1/2 (V
DD
− V
EE
)
p−p
, f
in
= 55 MHz
Channel Separation (Figure 6)
R
L
= 1 kW, V
in
= 1/2 (V
DD
− V
EE
)
p−p
, f
in
= 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7
R1 = 1 kW, R
L
= 10 kW, Control t
r
= t
f
= 20 ns
−
−
−
10
10
10
−
−
−
– 50
– 50
75
−
−
−
dB
dB
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
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