Freescale Semiconductor
Product Brief
Document Number: P2040PB
Rev. 0 , 11/2011
P2040 QorIQ
Communications Processor
Product Brief
This product brief provides an overview of the P2040
QorIQ communications processor features as well as
application use cases.
The P2040 combines four Power Architecture®
processor cores with high-performance datapath
acceleration logic and network and peripheral bus
interfaces required for networking, telecom/datacom,
wireless infrastructure, and military/aerospace
applications.
The P2040 is a very flexible device that can be
configured to meet many system application needs. For
example, it can be used for combined control, datapath,
and application layer processing in routers, switches,
base station controllers, and general-purpose embedded
computing systems. Its high level of integration offers
significant performance benefits compared to multiple
discrete devices, while also greatly simplifying board
design.
Contents
1
2
3
4
5
P2040 Application Use Cases. . . . . . . . . . . . . . . . . . . . . . 2
P2040 Multicore Processing Options . . . . . . . . . . . . . . . . 3
P2040 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Developer Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document Revision History. . . . . . . . . . . . . . . . . . . . . . . 29
© 2011 Freescale Semiconductor, Inc. All rights reserved.
P2040 Application Use Cases
1
1.1
P2040 Application Use Cases
Integrated Access Router (IAD)
Dual SATA ports provide high-speed, low-cost storage options for statistics or large databases. Compared
to SGMII, 2.5-Gb/s Ethernet enables the next step in performance connectivity to switches.
GE
Front panel access
SATA
Flash code upgrade
USB
GE
Out-of-band control path
P2040
PCIe
PCIe
PCIe peripherals
Front Panel
2.5 Gb/s SGMII,
PCIe
PCI Switch
24x GE
GE Switch
Data path
Figure 1. P2040 Integrated Access Router Interface
1.2
Base Station Network Interface Card (NIC)
Dual Serial RapidIO ports (up to 5 GHz) can be used for redundancy or multiple connections, both to the
backplane or to the DSP farm. With improved Type 11 messaging and new support for Type 9 data
streaming, the Serial RapidIO interconnect can now be used not only as a control plane interface, but can
also achieve its intended potential as a highly-efficient, data path.
DSP
DSP
P2040
SRIO Switch
RF components to
cellular user equipment
DSP
(MSC8156)
GE
SGMII,
2.5 Gb/s SGMII
Maintenance
Backhaul to access gateway
Figure 2. P2040 LTE Wireless Base Station Interface
P2040 QorIQ Communications Processor Product Brief, Rev. 0
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Freescale Semiconductor
Backplane
PCIe
P2040 Multicore Processing Options
2
2.1
P2040 Multicore Processing Options
Running on an OS
The four P2040 cores can run either on an OS or run OS-less using a simple scheduler.
There are different multi-processing options with the P2040 cores running on an OS:
• Four-core, asymmetric multi-processing
— Four copies of the same uni-processor operating system
or
— Up to four different uni-processor operating systems
• Four-core, symmetric multi-processing (SMP)
• Mixed symmetric and asymmetric multi-processing. For example,
N
cores running in SMP mode,
while the remainder of the cores operate asymmetrically with up to 4–N different OSes
CPU cores operating asymmetrically can be run at asynchronous clock rates. Each processor can source
its input clock from one of the multiple PLLs inside the P2040. This allows each core to operate at the
minimum frequency required to perform its assigned function, saving power. The cores are also capable
of running at half and quarter ratios of their input PLL frequency, and can switch between PLLs and ratios
nearly instantaneously. This allows lightly utilized CPUs to be slowed (under software control) for power
savings, rather than performing more complex task migration operations.
2.2
DPAA Multicore Processing Use Cases
Figure 3
shows several multicore processing use cases and the potential interaction with the Data Path
Acceleration Architecture (DPAA).
P2040 QorIQ Communications Processor Product Brief, Rev. 0
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3
P2040 Multicore Processing Options
A
SMP
All CPUs are running a single operating system, with any specialization of CPU
function occurring through OS techniques such as Task Affinity. The I/Os and
acceleration hardware are under the control of the SMP OS. Typically all CPUs
operate at the same frequency.
DPAA
B
SMP
Some number of the cores are operated as an SMP cluster, most likely running
high complexity control plane operations. The control plane configures and
manages the remaining processors, which are running individual copies of an
RTOS or scheduler to perform dataplane operations. In this use case, the SMP
CPUs typically operate at the same frequency, the remaining CPUs can run at a
different frequency from the SMP CPUs, and even from each other.
DPAA
C
CTL
A single CPU is used as the control processor, configuring and managing the
other three processors, which are running individual copies of an RTOS or
scheduler, as in B. CPU operating frequencies are an independent parameter.
DPAA
D
All CPUs are used for datapath operations, here shown as two sets of pipelined
functions, each interacting independently with the I/Os and accelerators.
Operating frequencies for each CPU in the pipeline can be set independently.
DPAA
Figure 3. CPU Usage Use Cases
Figure 4
shows an additional use case, which involves the use of one of the CPUs as an I/O processor. The
DPAA can greatly simplify and accelerate processing for packets entering the system by means of the
P2040 QorIQ Communications Processor Product Brief, Rev. 0
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Freescale Semiconductor
P2040 Features
Ethernet interfaces. For systems requiring external ASICs or legacy network interface cards in the
high-performance datapath, system developers can allocate a CPU to help interwork between the native
data buffers used by PCI Express- or Serial RapidIO-based network interfaces and the data buffers used
by the datapath acceleration hardware.
E
CTL
PCIe/
sRIO
ASIC
or
NIC
DPAA
Figure 4. IO Processor Managing PCIe/Serial RapidIO-Based Network Interfaces
3
3.1
P2040 Features
P2040 Block Diagram
Figure 5
shows the major functional units within the P2040.
P2040
Power Architecture®
e500mc Core
32-Kbyte 32-Kbyte
D-Cache I-Cache
eOpenPIC
PreBoot
Loader
Security
Monitor
Internal
BootROM
Power Mgmt
eSDHC
eSPI
2x DUART
4x I
2
C
2x
USB 2.0 PHY
Clocks/Reset
GPIO
CCSR
Test
Port/
SAP
eLBC
SATA 2.0
Pattern Match
Engine 2.1
RapidIO Msg
Mgr (RMan)
Buffer
Mgr
Security 4.2
Queue
Mgr
PAMU
PAMU
1024--Kbyte
Frontside CoreNet
Platform Cache
64-bit DDR3/3L
Memory Controller
CoreNet™
Coherency Fabric
PAMU
Peripheral
PAMU Access Mgmt Unit
Frame Manager
Parse, Classify,
Distribute
Buffer
1GE 1GE
1GE
1GE 1GE
DMA
DMA
Real Time Debug
Watchpoint
Cross
Trigger
Perf CoreNet
Monitor Trace
Aurora
PCIe PCIe
PCIe
sRIO sRIO
10-lane 5-GHz SerDes
Figure 5. P2040 Preliminary Block Diagram
P2040 QorIQ Communications Processor Product Brief, Rev. 0
Freescale Semiconductor
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