ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8752 is a low voltage, low skew LVCMOS clock
generator. With output frequencies up to 240MHz, the
ICS8752 is targeted for high performance clock applcations.
Along with a fully integrated PLL, the ICS8752 contains
frequency configurable outputs and an external feedback
input for regenerating clocks with “zero delay”.
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which refer-
ence clock is used. The output divider values of Bank A and
B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,
respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The
effective fanout of each output can be doubled by
utilizing the ability of each output to drive two series
terminated transmission lines.
F
EATURES
•
Fully integrated PLL
•
Eight LVCMOS outputs, 7Ω typical output impedance
•
Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
•
Input/Output frequency range: 18.33MHz to 240MHz
at V
CC
= 3.3V ± 5%
•
VCO range: 220MHz to 480MHz
•
External feedback for “zero delay” clock regeneration
•
Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
•
Output skew: 100ps (maximum)
•
Bank skew: 55ps (maximum)
•
Full 3.3V or 2.5V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
B
LOCK
D
IAGRAM
PLL_SEL
PLL
FB_IN
CLK0
0
CLK1
1
CLK_SEL
DIV_SELA1
DIV_SELA0
00
01
10
11
PHASE
DETECTOR
VCO
1
0
÷2
÷4
÷6
÷8
÷12
00
01
10
11
P
IN
A
SSIGNMENT
PLL_SEL
GND
GND
V
DDO
QB3
QB2
V
DD
nc
32 31 30 29 28 27 26 25
QA0
QA1
QA2
QA3
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
QB0
QB1
QB2
QB3
CLK_SEL
V
DDA
V
DD
CLK1
GND
QA0
QA1
V
DDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
GND
QB1
QB0
V
DDO
V
DDO
QA3
QA2
GND
ICS8752
21
20
19
18
17
GND
FB_IN
DIV_SELB1
DIV_SELB0
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
8752CY
www.idt.com
1
REV. C JULY 2, 2010
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7, 13, 17,
24, 28, 29
8
9
10
11, 32
12
14, 15,
18, 19
16, 20,
21, 25
22, 23,
26, 27
30
31
Name
DIV_SELB0,
DIV_SELB1
DIV_SELA0,
DIV_SELA1
MR/nOE
CLK0
GN D
FB_IN
CLK_SEL
V
DDA
V
DD
CLK1
QA0, QA1,
QA2, QA3
V
DDO
QB0, QB1,
QB2, QB3
nc
PLL_SEL
Type
Input
Input
Input
Input
Power
Input
Input
Power
Power
Input
Output
Power
Output
Unused
Input
Pullup
Pulldown
Description
Determines output divider values for Bank B as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Determines output divider values for Bank A as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
When logic HIGH, the internal dividers are reset and the outputs are
Pulldown disabled. When logic LOW, the master reset is disabled and the outputs
are enabled. LVCMOS / LVTTL interface levels.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Power supply ground.
Feedback input to phase detector for generating clocks with "zero delay".
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pins.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
Bank B clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
No connect.
Selects between the PLL and CLK0 or CLK1 as the input to the dividers.
When HIGH selects PLL. When LOW selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
V
DDA
, V
DD
, V
DDO
= 3.465V
23
7
Maximum
Units
pF
kΩ
kΩ
pF
Ω
8752CY
www.idt.com
2
REV. C JULY 2, 2010
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
DIV_
SELA1
X
0
0
1
1
0
0
1
1
0
0
1
1
Outputs
DIV_
SELA0
X
0
1
0
1
0
1
0
1
0
1
0
1
DIV_
SELB1
X
0
0
1
1
0
0
1
1
0
0
1
1
DIV_
SELB0
X
0
1
0
1
0
1
0
1
0
1
0
1
QAx
Hi-Z
fVCO/2
fVCO/4
fVCO/6
fVCO/8
fCLK0/2
fCLK0/4
fCLK0/6
fCLK0/8
fCLK1/2
fCLK1/4
fCLK1/6
fCLK1/8
QBx
Hi-Z
fVCO/4
fVCO/6
fVCO/8
fVCO/12
fCLK0/4
fCLK0/6
fCLK0/8
fCLK0/12
fCLK1/4
fCLK1/6
fCLK1/8
fCLK1/12
MR/nOE
1
0
0
0
0
0
0
0
0
0
0
0
0
PLL_SEL
X
1
1
1
1
0
0
0
0
0
0
0
0
CLK_SEL
X
X
X
X
X
0
0
0
0
1
1
1
1
NOTE: For normal operation, MR/nOE is LOW. When MR/nOE is HIGH, all ouputs are disabled.
T
ABLE
4A. QA O
UTPUT
F
REQUENCY W
/FB_IN = QB
Inputs
FB_IN
DIV_
DIV_
SELB1 SELB0
QB Output
Divider Mode
(NOTE 2)
CLK0, CLK1 (MHz)
(NOTE 1)
Minimum Maximum
DIV_
SELA1
0
QB
0
0
÷4
55
120
0
1
1
0
QB
0
1
÷6
36.66
80
0
1
1
0
QB
1
0
÷8
27.5
60
0
1
1
0
QB
1
1
÷
12
18.33
40
0
1
1
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QA output frequency equal to CLKx frequency times the multiplier ;
QB output frequency equal to CLKx.
8752CY
Outputs
DIV_
SELA0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
QA Output
Divider Mode
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
÷2
÷4
÷6
÷8
QA Multiplier
(NOTE 2)
2
1
0.667
0.5
3
1.5
1
0.75
4
2
1.33
1
6
3
2
1.5
www.idt.com
3
REV. C JULY 2, 2010
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
T
ABLE
4B. QB O
UTPUT
F
REQUENCY W
/FB_IN = QA
QA Output
Divider Mode
(NOTE 2)
÷2
Inputs
CLK0, CLK1 (MHz)
(NOTE 1)
Minimum Maximum
Outputs
DIV_
SELB1
0
QA
0
0
110
240
(NOTE 3)
0
1
1
0
QA
0
1
÷4
55
120
0
1
1
0
QA
1
0
÷6
36.66
80
0
1
1
0
QA
1
1
÷8
27.5
60
0
1
1
NOTE 1: VCO frequency range is 220MHz to 480MHz.
NOTE 2: QB output frequency equal to CLKx frequency times the multiplier ;
QA output frequency equal to CLKx.
NOTE 3: Maximum frequency of 240MHz valid for V
CC
= 3.3V ± 5% only.
DIV_
SELB0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
QB Output
Divider Mode
÷4
÷6
÷8
÷
12
÷4
÷6
÷8
÷
12
÷4
÷6
÷8
÷
12
÷4
÷6
÷8
÷
12
QB Multiplier
(NOTE 2)
0.5
0.333
0.25
0.167
1
0.667
0.5
0.333
1.5
1
0.75
0.5
2
1.333
1
0.667
FB_IN
DIV_
SELA1
DIV_
SELA0
8752CY
www.idt.com
4
REV. C JULY 2, 2010
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
105
15
20
Units
V
V
V
mA
mA
mA
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
100
15
20
Units
V
V
V
mA
mA
mA
8752CY
www.idt.com
5
REV. C JULY 2, 2010
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