DATASHEET
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
Recommended Applications
PCIe Gen1-2-3 Synthesizer for Common and
SRNS-clocked systems
IDT5V41315
Features/Benefits
•
16-pin TSSOP or VFQFPN package; small board
footprint
•
Outputs can be terminated to LVDS; can drive a wider
General Description
The IDT5V41315 is a PCIe Gen1-2-3 clock synthesizer
suitable for use in both Common-Clocked and Separate
Reference clock with No Spread (SRNS) timing
architectures. The IDT5V41315 uses a 25MHz input to
generate 4 different output frequencies. The output
frequency is selectable via select pins.
variety of devices
•
OE control pin; greater system power management
•
Industrial temperature range available; supports
demanding embedded applications
Key Specifications
•
•
•
•
•
Cycle-to-cycle jitter: 80ps
Output-to-output skew: <50 ps
PCIe Gen2 phase jitter: <3.0ps RMS (Common Clock)
PCIe Gen3 phase jitter: <1.0ps RMS (Common Clock)
Low Phase Noise: 12KHz to 20MHz <6ps RMS
Output Features
•
2 - 0.7V current mode differential HCSL output pairs
Block Diagram
VDD
2
CLK0
S1:S0
2
Control
Logic
Phase Lock Loop
CLK1
CLK1
CLK0
X1/ICLK
25 MHz
crystal or clock X2
Clock
Buffer/
Crystal
Oscillator
2
GND
OE
Optional tuning crystal
capacitors
Rr(IREF)
IDT®
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
1
IDT5V41315
MAY 8, 2017
IDT5V41315
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
Pin Assignments
VDDXD
S0
S1
NC
X1/ICLK
X2
OE
GNDXD
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDXD
CLK0
CLK0
GNDODA
VDDODA
CLK1
CLK1
IREF
16 15 14 13
S1
NC
X1/CLK
X2
1
2
3
4
CLK0#
12
11
10
9
8
IREF
GNDODA
VDDODA
CLK1
CLK1#
5V41315
5
OE
6
GNDXD
7
NC
16-pin (173 mil) TSSOP
16-pin VFQFPN
Output Select Table 1 (MHz)
S1
0
0
1
1
S0
0
1
0
1
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
Pin Descriptions
VFQFPN TSSOP Pin
Pin Name Pin Type Pin Description
Pin Number Number
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S0
S1
NC
X1/ICLK
X2
OE
GNDXD
NC
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
Input
Input
--
Input
Output
Input
Power
--
Output
Output
Output
Power
Power
Output
Output
Power
Select pin 0. See Table1. Internal pull-up resistor.
Select pin 1. See Table 1. Internal pull-up resistor.
No connect.
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Crystal connection. Leave unconnected for clock input.
Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor.
Connect to ground.
No connect.
Precision resistor attached to this pin is connected to the internal current reference,
typically 475 ohm.
HCSL complementary clock output 1.
HCSL true clock output 1.
Connect to voltage supply +3.3 V for output driver and analog circuits
Connect to ground.
HCSL complementary clock output 0.
HCSL true clock output 0.
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT®
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
2
CLK0
S0
IDT5V41315
MAY 8, 2017
IDT5V41315
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41315. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDXD, VDDODA
All Inputs and Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Protection (Input)
4.6 V
Rating
-0.5 V to VDD+0.5 V
-65 to +150C
125C
260C
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
T
A
= T
AMBIENT
Parameter
Supply Voltage
Ambient Operating
Temperature
Input High Voltage
1
Input Low Voltage
1
Symbol
V
Conditions
Min.
3.135
-40
2.2
VSS-0.3
-5
Typ.
3.3
+25
Max.
3.465
+85
VDD +0.3
0.8
5
Units
V
°C
V
V
A
mA
mA
pF
pF
pF
nH
k
k
T
AMBIENT
Industrial Temperature range
V
IH
V
IL
I
IL
I
DD
I
DDOE
C
IN
C
OUT
C
INX
L
PIN
Z
O
R
PU
CLK outputs
S0, S1, OE
S0, S1, OE, ICLK
S0, S1, OE, ICLK
0 < Vin < VDD
R
S
=33R
P
=50, C
L
=2 pF
OE =Low
Input pin capacitance
Output pin capacitance
Input Leakage Current
2
Operating Supply Current
@100 MHz
Input Capacitance
Output Capacitance
X1, X2 Capacitance
Pin Inductance
Output Impedance
Pull-up Resistor
63
42
85
50
7
6
5
5
3.0
100
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
IDT®
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
3
IDT5V41315
MAY 8, 2017
IDT5V41315
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V ±5%, T
A
= T
AMBIENT
Parameter
Input Frequency
Output Frequency
Output High Voltage
1,2
Output Low Voltage
1,2
Crossing Point Voltage
1,2
Crossing Point
Voltage
1,2,4
Jitter, Cycle-to-Cycle
1,3
Frequency Synthesis Error
Rise Time
1,3
Fall Time
1,3
Rise/Fall Time
Duty Cycle
1,3
Output Enable Time
5
Output Disable Time
5
Stabilization Time
Variation
1,2
Output to Output Skew
Symbol
Conditions
HCSL termination
LVDS termination
Min.
25
25
-150
250
Typ.
25
Max.
200
100
850
550
140
80
Units
MHz
MHz
MHz
mV
mV
mV
mV
ps
ppm
V/ns
V/ns
ps
ps
%
ns
ns
ms
V
OH
V
OL
HCSL
HCSL
Absolute
Variation over all edges
All outputs
0
1
1
t
OR
t
OF
±150mV
±150mV
4
4
125
50
45
All outputs
All outputs
t
STABLE
From power-up VDD=3.3 V
50
50
55
100
100
1.8
Note 1: Test setup is R
S
=33R
P
=50 with C
L
=2 pF, Rr = 475 (1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter Parameters
T
A
= T
AMBIENT
, Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Symbol
t
jphaseG1
t
jphaseG2Lo
Jitter, Phase
t
jphaseG2High
t
jphaseG3
t
jphase12K20M
1
Conditions
PCIe Gen 1
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
12kHz-20MHz
Min
Typ
32
0.7
2.3
0.6
Max
86
3
3.1
1
N/A
Units
ps (p-p)
ps
(RMS)
ps
(RMS)
ps
(RMS)
ps
(RMS)
Notes
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Guaranteed by design and characterization, not 100% tested in production.
2
See http://www.pcisig.com for complete specs
3
Applies to 100MHz
IDT®
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
4
IDT5V41315
MAY 8, 2017
IDT5V41315
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the IDT5V41315 to
meet PCI Express specifications.
R
R
475
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R
R
= 475
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41315 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the
PCI-Express Layout Guidelines
section.
The IDT5V41315 can also be configured for LVDS
compatible voltage levels. See the
LVDS Compatible
Layout Guidelines
section.
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41315.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
IDT®
2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER
5
IDT5V41315
MAY 8, 2017
京公网安备 11010802033920号
EEWORLD
