The DG535/536 are 16-channel multiplexers designed for
routing one of 16 wideband analog or digital input signals to
a single output. They feature low input and output
capacitance, low on-resistance, and n-channel DMOS “T”
switches, resulting in wide bandwidth, low crosstalk and high
“off” isolation. In the on state, the switches pass signals in
either direction, allowing them to be used as multiplexers or
as demultiplexers.
On-chip address latches and decode logic simplify
microprocessor interface. Chip Select and Enable inputs
simplify addressing in large matrices. Single-supply
operation and a low 75 µW power consumption vastly
reduces power supply requirements.
Theses devices are built on a proprietary D/CMOS process
which creates low-capacitance DMOS FETs and
high-speed, low-power CMOS logic on the same substrate.
For more information please refer to Vishay Siliconix
Application Note AN501 (FaxBack document number
70608).
FEATURES
•
•
•
•
•
•
•
Crosstalk: - 100 dB at 5 MHz
300 MHz Bandwidth
Low Input and Output Capacitance
Low Power: 75 µW
Low r
DS(on)
: 50
Ω
On-Board Address Latches
Disable Output
Pb-free
Available
RoHS*
COMPLIANT
BENEFITS
•
•
•
•
•
High Video Quality
Reduced Insertion Loss
Reduced Input Buffer Requirements
Minimizes Power Consumption
Simplifies Bus Interface
APPLICATIONS
•
•
•
•
•
•
Video Switching/Routing
High Speed Data Routing
RF Signal Multiplexing
Precision Data Acquisition
Crosspoint Arrays
FLIR Systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
GND
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
DIS
CS
CS
EN
A
0
1
2
3
4
5
6
7
8
9
10
11
12
Latches/Decoders/Drivers
13
14
Top View
Dual-In-Line
Top View
16
15
A
2
A
1
DG535
DG536
28
27
26
25
24
23
22
21
20
19
18
17
S
9
GND
GND
S1
S
10
S
11
S
12
DIS
S
13
S
14
S
15
S
16
D
V+
ST
A
3
18 19 20 21 22 23 24 25 26 27 28
S
16
GND
S
15
GND
S
14
GND
S
13
GND
S
12
GND
GND
CS
CS
EN
A
0
A
1
A
2
A
3
ST
V+
D
7
8
9
10
11
12
13
14
15
16
17
Latches/
Decoders/
Drivers
39
38
37
36
35
34
33
32
31
30
29
S
6
GND
S
7
GND
S
8
GND
S
9
GND
S
10
GND
S
11
PLCC/Cerquad
GND
GND
S4
GND
S5
GND
S2
S3
6 5 4 3 2
1 44 43 42 41 40
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70070
S-71241–Rev. E, 25-Jun-07
www.vishay.com
1
DG535/536
Vishay Siliconix
ORDERING INFORMATION
Temperature Range
Package
28-Pin Plastic DIP
- 40 to 85 °C
44-Pin PLCC
Part Number
DG535DJ
DG535DJ-E3
DG536DN
DG536DN-E3
TRUTH TABLE
EN
0
X
X
CS
X
0
X
CS
X
X
1
ST
a
1
A
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
A
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
A
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Channel Selected
None
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
11
S
12
S
13
S
14
S
15
S
16
Maintains previous switch condition
Disable
b
High Z
1
1
0
1
Low Z
X
X
X
Logic "0" = V
AL
≤
4.5 V
Logic "1" = V
AH
≥
10.5 V
X = Do not Care
0
High Z or Low Z
Notes:
a. Strobe input (ST) is level triggered.
b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected.
ABSOLUTE MAXIMUM RATINGS
Parameter
V+ to GND
Digital Inputs
V
S
, V
D
Current (any terminal) Continuous
Current (S or D) Pulsed 1 ms 10 % duty cycle
(A Suffix)
Storage Temperature
(D Suffix)
Power Dissipation (Package)
a
28-Pin Plastic DIP
b
28-Pin Sidebraze
c
44-Pin PLCC
d
44-Pin Cerquad
e
Limit
- 0.3 to + 18
(GND - 0.3) to (V+) + 2
or 20 mA, whichever occurs first
(GND - 0.3) to (V+) + 2
or 20 mA, whichever occurs first
20
40
- 65 to 150
- 65 to 125
625
1200
450
825
Unit
V
mA
°C
mW
Notes:
a. All leads soldered or welded to PC board.
b. Derate 8.6 mW/°C above 75 °C.
c. Derate 16 mW/°C above 75 °C.
d. Derate 6 mW/°C above 75 °C.
e. Derate 11 mW/°C above 75 °C.
www.vishay.com
2
Document Number: 70070
S-71241–Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, ST, CS = 10.5 V
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source
On-Resistance
Resistance Match
Source Off Leakage Current
Drain On Leakage Current
Disable Output
Digital Control
Input Voltage High
Input Voltage Low
Address Input Current
Address Input Capacitance
Dynamic Characteristics
PLCC
On State Input Capacitance
e
C
S(on)
V
D
= V
S
= 3 V
Cerquad
DIP
PLCC
Off State Input Capacitance
e
C
S(off)
V
S
= 3 V
Cerquad
DIP
Off State Output
Capacitance
e
Multiplexer Switching Time
Break-Before-Make Interval
EN, CS, CS, ST, t
ON
EN, CS, CS, ST, t
OFF
Charge Injection
Single-Channel Crosstalk
PLCC
C
D(off)
t
TRANS
t
OPEN
t
ON
t
OFF
Q
X
TALK(SC)
V
D
= 3 V
Cerquad
DIP
See Figure 4
See Figure 2 and 3
See Figure 2
See Figure 5
R
IN
= 75
Ω,
R
L
= 75
Ω
f = 5 MHz
See Figure 9
R
IN
= R
L
= 75
Ω,
f = 5 MHz
EN = 4.5 V
See Figure 8
R
IN
= 10
Ω,
R
L
= 10 kΩ
f = 5 MHz
See Figure 10
R
IN
= 10
Ω,
R
L
= 10 kΩ
f = 5 MHz
See Figure 7
PLCC
Cerquad
DIP
PLCC
Cerquad
DIP
PLCC
Cerquad
DIP
PLCC
Cerquad
DIP
Room
Room
Room
Room
Room
Room
Room
Room
Room
Full
Full
Full
Full
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
Room
- 35
- 100
- 93
- 60
- 85
- 84
- 60
- 92
- 87
- 72
- 74
- 74
- 60
500
MHz
- 60
- 60
dB
25
300
150
32
35
40
2
5
3
8
12
9
300
25
300
150
pC
ns
300
20
20
55
8
55
8
pF
45
45
V
AIH
V
AIL
I
AI
C
A
V
A
= GND or V+
Full
Full
Room
Full
Full
< 0.01
5
10.5
-1
- 100
4.5
1
100
10.5
-1
- 100
4.5
1
100
V
µA
pF
Symbol
V
ANALOG
r
DS(on)
Δr
DS(on)
I
S(off)
I
D(on)
R
DISABLE
I
S
= - 1 mA, V
D
= 3 V, EN = 10.5 V
Sequence Each Switch On
V
S
= 3 V, V
D
= 0 V, EN = 4.5 V
V
S
= V
D
= 3 V, EN = 10.5 V
I
DISABLE
= 1 mA, EN = 10.5 V
CS = 4.5 V, V
A
= 4.5 or 10.5 V
f
Temp
b
Full
Room
Full
Room
Room
Full
Room
Full
Room
Full
55
Typ
c
A Suffix
- 55 to 125 °C
Min
c
0
Max
c
10
90
120
9
10
100
10
1000
200
250
D Suffix
- 40 to 85 °C
Min
c
0
Max
c
10
90
120
9
10
100
- 10
- 100
200
250
Unit
V
Ω
- 10
- 100
- 10
- 1000
100
- 10
- 100
- 10
- 100
nA
Ω
Chip Disabled Crosstalk
X
TALK(CD)
Adjacent Input Crosstalk
X
TALK(AI)
All Hostile Crosstalk
Bandwidth
e
X
TALK(AH)
BW
R
L
= 50
Ω,
See Figure 6
Document Number: 70070
S-71241–Rev. E, 25-Jun-07
www.vishay.com
3
DG535/536
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, ST, CS = 10.5 V
Parameter
Power Supplies
Positive Supply Current
Supply Voltage Range
Symbol
CS = 4.5 V, V
A
= 4.5 or 10.5 V
f
Temp
b
Room
Full
Full
Full
Full
See Figure 1
Full
50
50
Typ
c
5
10
200
100
A Suffix
- 55 to 125 °C
Min
c
Max
c
50
100
16.5
D Suffix
- 40 to 85 °C
Min
c
Max
c
50
100
16.5
Unit
I+
V+
Any One Channge I Selected with All
Logic Inputs at GND or V+
µA
V
10
200
100
Minimum Input Timing Requirements
t
SW
Strobe Pulse Width
A
0
, A
1
, A
2
, A
3
CS, CS, EN
Data Valid to Strobe
A
0
, A
1
, A
2
, A
3
CS, CS, EN
Data Valid after Strobe
t
DW
t
WD
ns
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. V
A
= input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
京公网安备 11010802033920号
EEWORLD
