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IS62WV6416ALL-55BI-TR

Description
SRAM 1M (64Kx16) 55ns Async SRAM
Categorystorage   
File Size230KB,17 Pages
ManufacturerISSI(Integrated Silicon Solution Inc.)
Websitehttp://www.issi.com/
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IS62WV6416ALL-55BI-TR Overview

SRAM 1M (64Kx16) 55ns Async SRAM

IS62WV6416ALL-55BI-TR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerISSI(Integrated Silicon Solution Inc.)
Product CategorySRAM
RoHSN
PackagingReel
Moisture SensitiveYes
Factory Pack Quantity2500
IS62WV6416ALL
IS62WV6416BLL
64K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 45ns, 55ns
• CMOS low power operation:
30 mW (typical) operating
15 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.7V--2.2V V
DD
(62WV6416ALL)
2.5V--3.6V V
DD
(62WV6416BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• 2CS Option Available
• Lead-free available
JANUARY 2008
DESCRIPTION
The
ISSI
IS62WV6416ALL/ IS62WV6416BLL are high-
speed, 1M bit static RAMs organized as 64K words by 16
bits. It is fabricated using
ISSI
's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH and both
LB
and
UB
are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62WV6416ALL and IS62WV6416BLL are packaged
in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and
44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
64K x 16
MEMORY ARRAY
V
DD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2008 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/14/08
1

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