Programmable Clock Generator
5P49V5925
DATASHEET
Description
The 5P49V5925 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Features
•
Generates up to four independent output frequencies
•
High-performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs
•
Four fractional output dividers (FODs)
•
Independent Spread Spectrum capability on each output
•
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
•
I
2
C serial programming interface
•
Five LVCMOS outputs, including one reference output
•
I/O Standards:
•
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 200MHz
– Crystal frequency range: 8MHz to 40MHz
•
Output frequency ranges:
•
•
•
•
•
•
•
•
•
•
– LVCMOS Clock Outputs – 1MHz to 200MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
Pin Assignment
OUT0_SEL_I2CB
V
DDO
0
V
DDO
1
OUT1
V
DDD
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
CLKSEL
1
2
3
4
5
6
24 23 22 21 20 19
18
17
NC
V
DDO
2
OUT2
NC
V
DDO
3
OUT3
NC
EPAD
GND
16
15
14
7
8
9
13
10 11 12
SEL1/SDA
SEL0/SCL
SD/OE
V
DDO
4
24-pin VFQFPN
5P49V5925 AUGUST 9, 2017
1
©2017 Integrated Device Technology, Inc.
OUT4
NC
5P49V5925 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
V
DDO
1
FOD1
CLKIN
CLKINB
FOD2
CLKSEL
SD/OE
FOD3
SEL1/SDA
V
DDO
4
SEL0/SCL
OTP
and
Control Logic
V
DDO
0
OUT0_SEL_I2CB
OUT1
V
DDO
2
OUT2
PLL
V
DDO
3
OUT3
FOD4
OUT4
V
DDA
V
DDD
Applications
•
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
PROGRAMMABLE CLOCK GENERATOR
2
AUGUST 9, 2017
5P49V5925 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
5
Name
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
Input
Input
Input
Input
Power
Type
Internal
Pull-down
Internal
Pull-down
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
Crystal Oscillator interface output.
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that
the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
Analog functions power supply pin. Connect to 1.8V to 3.3V. V
DDA
and V
DDD
should
have the same voltage applied.
Internal
Pull-down
Input clock select. Selects the active input reference source in manual switchover
mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE
pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW only when pin is configured as OE (Default is active
LOW.) Weak internal pull down resistor. When configured as SD, device is shut
down and the single-ended LVCMOS outputs are driven low. When configured as
OE, and outputs are disabled, the outputs can be selected to be tri-stated or driven
high/low, depending on the programming bits as shown in the SD/OE Pin Function
Truth table.
Configuration select pin, or I
2
C SDA input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Configuration select pin, or I
2
C SCL input as selected by OUT0_SEL_I2CB. Weak
internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT4.
Output Clock 4. Please refer to the Output Drivers section for more details.
No connect.
No connect.
Output Clock 3. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3.
No connect.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT2.
No connect.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1.
Digital functions power supply pin. Connect to 1.8 to 3.3V. V
DDA
and V
DDD
should
have the same voltage applied.
6
CLKSEL
Input
7
SD/OE
Input
Internal
Pull-down
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SEL1/SDA
SEL0/SCL
V
DDO
4
OUT4
NC
NC
OUT3
V
DDO
3
NC
OUT2
V
DDO
2
NC
OUT1
V
DDO
1
V
DDD
Input
Input
Power
Output
–
–
Output
Power
–
Output
Power
–
Output
Power
Power
Internal
Pull-down
Internal
Pull-down
AUGUST 9, 2017
3
PROGRAMMABLE CLOCK GENERATOR
5P49V5925 DATASHEET
Number
23
Name
V
DDO
0
Power
Type
Description
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage
levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9.
If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be
configured as hardware select pins, SEL1 and SEL0. If a weak pull down (10Kohms)
is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA
and SCL pins of an I
2
C interface. After power up, the pin acts as a LVCMOS
reference output.
Connect to ground pad.
24
OUT0_SEL_I2CB
Input/
Output
Internal
Pull-down
ePAD
GND
GND
PROGRAMMABLE CLOCK GENERATOR
4
AUGUST 9, 2017
5P49V5925 DATASHEET
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5925 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5925 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Table 4: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I
2
C programming as
shown in Table 4.
PRIMSRC
0
0
1
1
CLKSEL
0
1
0
1
Source
XIN/REF
CLKIN, CLKINB
CLKIN, CLKINB
XIN/REF
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Frequency–Fref
(MHz)
5
200
Loop
Bandwidth
Min (kHz)
40
300
Loop
Bandwidth
Max (kHz)
126
1000
PRIMSRC is bit 1 of Register 0x13.
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
OUT0_SEL_I2CB SEL1 SEL0
I
2
C
REG0:7 Config
@ POR
Access
1
1
1
1
0
0
0
0
1
1
X
X
0
1
0
1
X
X
No
No
No
No
Yes
Yes
0
0
0
0
1
0
0
1
2
3
I2C
defaults
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10mS of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDD/VDDA.
The SELx pins must be driven with a digital signal of < 300ns
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
AUGUST 9, 2017
5
PROGRAMMABLE CLOCK GENERATOR
stm32/stm8
京公网安备 11010802033920号
EEWORLD
