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841604AGI-01LFT

Description
Clock Synthesizer / Jitter Cleaner FemtoClock Crystal-to-0.7V
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size321KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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841604AGI-01LFT Overview

Clock Synthesizer / Jitter Cleaner FemtoClock Crystal-to-0.7V

841604AGI-01LFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP28,.3
Contacts28
Manufacturer packaging codeDQG28
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length9.7 mm
Humidity sensitivity level3
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency125 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency25 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate87 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
FemtoClock® Crystal-to-0.7V Differential
ICS841604I-01
DATA SHEET
General Description
The ICS841604I-01 is an optimized PCIe and sRIO clock generator.
The device uses a 25MHz parallel crystal to generate 100MHz and
125MHz clock signals, replacing solutions requiring multiple
oscillator and fanout buffer solutions. The device has excellent
phase jitter (< 1ps rms) suitable to clock components requiring
precise and low-jitter PCIe or sRIO or both clock signals. Designed
for telecom, networking and industrial applications, the
ICS841604I-01 can also drive the high-speed sRIO and PCIe
SerDes clock inputs of communication processors, DSPs, switches
and bridges.
Features
Four 0.7V differential HCSL outputs: configurable for PCIe
(100MHz) and sRIO (125MHz) clock signals
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input
Supports the following output frequencies: 100MHz or 125MHz
VCO: 500MHz
PLL bypass and output enable
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.5ps (typical)
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
XTAL_IN
Pin Assignment
REF_SEL
REF_IN
V
DD
GND
XTAL_IN
XTAL_OUT
MR
V
DD
OE3
OE2
OE1
OE0
GND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DDA
BYPASS
IREF
FSEL
V
DD
nQ3
Q3
nQ2
Q2
GND
nQ1
Q1
nQ0
Q0
OSC
XTAL_OUT
REF_IN
Pulldown
0
1
nQ0
M=
÷4
÷5
(default)
Pulldown
OE0
FemtoClock
PLL
1
VCO = 500MHz
0
Q1
nQ1
Pulldown
OE1
REF_SEL
Pulldown
M =
÷20
IREF
BYPASS
FSEL
Pulldown
Pulldown
Pulldown
OE2
Q2
nQ2
Q3
nQ3
Pulldown
OE3
MR
Pulldown
ICS841604I-01
28-Lead TSSOP, 240MIL
6.1mm x 9.7mm x 0.925
mm package body
G Package
Top View
ICS841604GI-01 REVISION A APRIL 10, 2012
1
©2012 Integrated Device Technology, Inc.
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