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854104AGLF

Description
Clock Buffer 4 LVDS OUTPUT BUFFER
Categorylogic    logic   
File Size338KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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854104AGLF Overview

Clock Buffer 4 LVDS OUTPUT BUFFER

854104AGLF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-16
Contacts16
Manufacturer packaging codePGG16
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTSSOP 4.4 MM 0.65MM PITCH
series854104
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup1.3 ns
propagation delay (tpd)1.3 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.05 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
Base Number Matches1
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
General Description
The ICS854104 is a low skew, high performance 1-to-4
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS), the ICS854104 provides a low power,
low noise, solution for distributing clock signals over controlled
impedances of 100. The ICS854104 accepts a differential input
level and translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make the
ICS854104 ideal for those applications demanding well defined
performance and repeatability.
ICS854104
DATASHEET
Features
Four differential LVDS output pairs
One differential clock input pair
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Each output has an individual OE control
Maximum output frequency: 700MHz
Translates differential input signals to LVDS levels
Additive phase jitter, RMS: 0.232ps (typical)
Output skew: 50ps (maximum)
Part-to-part skew: 350ps (maximum)
Propagation delay: 1.3ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
Q0
nQ0
Pullup
Pin Assignment
OE0
OE1
OE2
V
DD
GND
CLK
nCLK
OE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
OE0
Q1
nQ1
CLK
Pulldown
nCLK
Pullup/Pulldown
Pullup
OE1
Q2
nQ2
ICS854104
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
Pullup
OE2
Q3
nQ3
Pullup
OE3
ICS854104AG REVISION A JANUARY 30, 2014
1
©2014 Integrated Device Technology, Inc.
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