PI49FCT3802/PI49FCT3803
1:5/1:7 Clock Buffer
for Networking Applications
Features
• High Frequency >156 MHz
• High-speed, low-noise, non-inverting buffer
- PI49FCT3802 is 1:5 buffer
- PI49FCT3803 is 1:7 buffer
• Low-skew (<250ps) between any two output clocks
• Low duty cycle distortion <250ps
• Low propagation delay <2.5ns
• 5V Tolerant input
• Multiple V
DD
, GND pins for noise reduction
• 3.3V supply voltage
• Packaging (Pb-free & Green available):
- 16-pin TSSOP (L)
- 16-pin QSOP (Q)
Description
The PI49FCT380x is a 3.3V compatible, high-speed, low-noise
non-inverting clock buffer. The key goal in designing the
PI6C380x is to target networking applications that require low-
skew, low-jitter, and high-frequency clock distribution. Providing
output-to-output skew as low as 250ps, the PI49FCT380x is an
ideal clock distribution device for synchronous systems. Designing
synchronous networking systems requires a tight level of skew from
a large number of outputs.
Pin Description
Pin Name
3802
BUF_IN
CLK[0:4]
GND
V
DD
3803
BUF_IN
CLK[0:4]
GND
V
DD
Description
Input
Outputs
GND
Power
Block Diagram (PI49FCT3802)
CLK0
Pin Configuration (PI49FCT3802)
BUF_IN
GND
1
2
3
4
5
6
7
8
16
15
VDD
CLK4
CLK3
GND
CLK1
BUF_IN
CLK2
CLK0
VDD
CLK1
16-Pin
L, Q
14
13
12
11
10
9
CLK2
VDD
NC
GND
CLK3
GND
NC
CLK4
VDD
Block Diagram (PI49FCT3803)
CLK0
Pin Configuration (PI49FCT3803)
BUF_IN
GND
CLK0
CLK2
1
2
3
4
5
6
7
8
16
15
VDD
CLK1
BUF_IN
CLK6
CLK5
GND
VDD
CLK1
16-Pin
L, Q
14
13
12
11
10
9
CLK4
VDD
CLK3
GND
CLK3
GND
CLK2
CLK6
VDD
1
PS8559A
09/14/04
PI49FCT3802/PI49FCT3803
1:5/1:7 Clock Buffers
for Networking Applications
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature...........................................................–65°C to +150°C
V
DD
Voltage ............................................................................ –0.5V to 5.5V
Output Voltage......................................................................... –0.5V to 5.5V
Input Voltage ........................................................................... –0.5V to 5.5V
DC Output Current ............................................................–60mA to +60mA
Power Dissipation ............................................................................. 500mW
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional op-
eration of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Operating Range
V
DD
Voltage ............................................................................... 3.3V ± 0.3V
Commercial Temperature .........................................................0°C to +70°C
Industrial Temperature .........................................................–40°C to +85°C
Input Frequency ................................................................... DC to 156 MHz
Capacitive Loading .................................................................. 10pF to 50pF
DC Electrical Characteristics
(Over the Operating Range)
Parameters
V
IH
V
IL
I
IH
I
IL
V
IK
V
OH
V
OL
I
OH
I
OL
Description
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Current
Output LOWCurrent
Test Conditions
(1)
Guaranteed Logic HIGH Level (Input Pins)
Guaranteed Logic LOW Level (Input Pins)
V
DD
=
Max.
V
DD
=
Max.
V
DD
=
Min.,
I
IN
= –18mA
V
CC
= Min.,
V
IN
= V
IH
or
V
IL
V
CC
= Min.,
V
IN
= V
IH
or
V
IL
I
OH
= –0.1mA
I
OH
= –12mA
I
OH
= 0.1mA
I
OH
= 12mA
V
DD
-0.2
2.4
(3)
V
IN
= V
DD
V
IN
= GND
Min.
2.0
-0.5
Typ.
(2)
Max.
5.5
0.8
1
-1
Units
V
µA
-0.7
3.0
-1.2
V
0.2
0.5
-180
200
mA
0.3
-45
50
-75
92
V
DD
= 3.0V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(4)
V
DD
= 3.0V, V
IN
= V
IH
OR
V
IL
, V
OUT
= 1.5V
(4)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
DD
= 3.3V, +25°C ambient and maximum loading.
3. V
OH
= V
DD
– 0.6V at rated current.
4. This parameter is determined by device characterization but is not production tested.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
2
PS8559A
09/14/04
PI49FCT3802/PI49FCT3803
1:5/1:7 Clock Buffers
for Networking Applications
Power Supply Characteristics
Parameters
I
DDQ
∆I
DD
Description
Quiescent Power Supply Current
Supply Current per Inputs
@ TTL High
Test Conditions
V
DD
= Max.
V
DD
= Max.
V
IN
= GND or V
DD
V
IN
= V
DD
-0.6V(3)
50 MHz
67 MHz
I
DD
Dynamic Supply Current
V
DD
= 3.6V,
No load
80 MHz
100 MHz
125 MHz
156 Mhz
Min.
Typ.
(2)
0.1
47
43
56
66
81
97
121
Max.
30
300
Units
µA
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
DD
= 3.3V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
DD
– 0.6V); all other inputs at V
DD
or GND.
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
3.0
—
Max.
4
6
Units
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
Switching Characteristics
(V
DD
= 3.3V ± 0.3V, T
A
= 85°C)
Parameters
t
R
/t
F
t
PLH
t
PHL
t
sk(o)(3)
t
sk(p)(3)
t
sk(t)(3)
Desciription
CLKn Rise/Fall Time 0.8V ~ 2.0V
Propagation Delay BUF_IN to CLKn
Skew between two outputs of the same package (same
transition)
Skew between opposite transitions (t
PHL
- t
PLH
) of the same
output
Skew between two outputs of different packages
(4)
C
L
= 15pF,
125 Mhz
1.0
Test Conditions
Min.
Typ.
0.7
2.2
110
200
Max.
1.0
2.5
250
ps
250
0.55
ns
ns
Units
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worse cast temperature (max. temp).
4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
3
PS8559A
09/14/04
PI49FCT3802/PI49FCT3803
1:5/1:7 Clock Buffers
for Networking Applications
Switching Waveforms
Propagation Delay
3V
Input
t
PLH
Output
t
R
Pulse Skew – t
SK(P)
3V
Input
t
PLH
Output
t
PHL
1.5V
t
PHL
1.5V
0V
V
OH
1.5V
V
OL
t
SK(p)
=
|
t
PHL
– t
PLH
|
0V
V
OH
2.0V
0.8V
1.5V
V
OL
t
F
Output Skew – t
SK(O)
3V
Input
t
PLHx
CLKx
t
SK(o)
CLKy
t
PLHy
t
PHLy
Package Skew – t
SK(T)
3V
Input
t
PLH1
1.5V
t
PHLx
1.5V
0V
V
OH
1.5V
t
SK(o)
t
PHL1
0V
Package 1
Output
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
SK(t)
t
SK(t)
V
OL
Package 2
Output
V
OH
1.5V
t
PLH2
t
PHL2
V
OL
t
SK(o)
=
t
PLHy
– t
PLHx
or
t
PHLy
– t
PHLx
t
SK(t)
=
t
PLH2
– t
PLH1
or
t
PHL2
– t
PHL1
Test Circuits for All Outputs
V
DD
Pulse
Generator
V
IN
V
OUT
D.U.T.
CL
Definitions:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance, should be equal to Zout of the
Pulse Generator.
4
PS8559A
09/14/04
PI49FCT3802/PI49FCT3803
1:5/1:7 Clock Buffers
for Networking Applications
Packaging Mechanical:
16-Pin QSOP (Q)
16
.008
0.20
MIN.
.150
.157
3.81
3.99
.008
.013
0.20
0.33
Guage Plane
.010
0.254
1
.189
.197
4.80
5.00
Detail A
.016
.035
0.41
0.89
.041
1.04
REF
0˚-6˚
.015 x 45°
0.38
.053
1.35
.069
1.75
SEATING
PLANE
Detail A
.008
0.203
REF
.007
.010
0.178
0.254
0.41
.016
1.27
.050
.228
.244
5.79
6.19
.025
BSC
0.635
.008
.012
0.203
0.305
.004
0.101
.010
0.254
X.XX
DENOTES DIMENSIONS IN MILLIMETERS
X.XX
Packaging Mechanical: 16-Pin TSSOP (L)
16
.169
.177
4.3
4.5
1
.193
.201
4.9
5.1
.004
.008
.047
max.
1.20
0.09
0.20
0.45
.018
0.75
.030
SEATING
PLANE
.252
BSC
6.4
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
.006
0.05
0.15
5
PS8559A
09/14/04
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