21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Product Features
• Operating Frequency up to 220 MHz for PC3200 Registered
DIMM applications
• Distributes one differential clock input pair to ten differential
clock output pairs
• Inputs (CLK,CLK) and (FBIN,FBIN)
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT)
• External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input
• Operates at 2.5V for PC1600, PC2100, PC2700,
and 2.6V for PC3200
• Packaging (Pb-free & Green available):
– 48-pin TSSOP
Product Description
PI6CVF857 PLL clock device is developed for registered DDR DIMM
applications. The device is a zero-delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten differential pairs of
clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN), and the Analog Power input (AV
DD
).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off, and the differential clock
outputs are 3-stated. When the AV
DD
is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. An input frequency detection circuit will
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CVF857 clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]).
The PI6CVF857 is also able to track Spread Spectrum Clocking for
reduced EMI.
Block Diagram
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
PWRDWN
AVDD
Powerdown
and Test
Logic
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
CLK
CLK
FBIN
FBIN
PLL
08-0298
1
PS8683D
11/12/08
V
DDQ
Y5
V
DDQ
Y1
Y1
Y6
Y0
Y0
GND
Y2
Y2
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
1
2
3
4
5
6
7
8
9
40 39 38 37 36 35 34 33 32 31
Y5
Y6
Y9
V
DDQ
Y3
Y3
Y4
Y4
Y9
Y8
08-0298
2
V
DDQ
Y8
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Pin Configuration TSSOP ( A)
GND
Y0
Y0
VD D Q
Y1
Y1
GND
GND
Y2
Y2
VD D Q
VD D Q
CLK
CLK
VD D Q
AV D D
AGND
GND
Y3
Y3
VD D Q
Y4
Y4
GND
48
1
2
47
46
3
45
4
44
5
43
6
7
42
41
8
40
9
10
48-Pin
39
38
11
A
37
12
36
13
35
14
34
15
16
33
32
17
31
18
30
19
29
20
28
21
22
27
23
26
24
25
GND
Y5
Y5
VD D Q
Y6
Y6
GND
GND
Y7
Y7
VD D Q
PWRDWN
FBIN
FBIN
VD D Q
FBOUT
FBOUT
GND
Y8
Y8
VD D Q
Y9
Y9
GND
Pin Configuration TQFN (ZD)
30
29
28
27
26
25
24
23
22
Y7
Y7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
V
DDQ
FBOUT
FBOUT
GND
10
21
11 12 13 14 15 16 17 18 19 20
PS8683D
10/06/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Pinout Table
Pin Name
CLK
CLK
Yx
Yx
FBOUT
FBOUT
FBIN
FBIN
PWRDWN
V
DDQ
AV
DD
AGND
GND
Reference Clock input
Clock outputs.
Complement Clock outputs.
Feedback output, and Complement Feedback Output
Feedback Input, and Complement Feedback Input
Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and
the differential clock outputs are disabled to a - state. When PWRDWN = 1, all differential clock outputs are
enabled and run at the same frequency as CLK.
Power Supply for I/O.
Analog /core power supply. AV
DD
can be used to bypass the PLL for testing purposes. When AV
DD
is strapped to
ground, PLL is bypassed and CLK is buffered directly to the device outputs.
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
De s cription
Function Table
Inputs
AV
DD
GND
GND
X
X
Nominal
(2)
Nominal
(2)
Nominal
(2)
PWRDWN
H
H
L
L
H
H
X
CLK
L
H
L
H
L
H
CLK
H
L
H
L
H
L
Y
L
H
Z
Z
L
H
Z
Y
H
L
Z
Z
H
L
Z
Outputs
FBOUT
L
H
Z
Z
L
H
Z
FBOUT
H
L
Z
Z
H
L
Z
Bypassed/off
Bypassed/off
off
off
on
on
off
PLL
< 20 MHz
(1)
Notes:
1. For testing and power saving purposes, PI6CVF857 will power down if the frequency of the reference inputs CLK, CLK is well below the
operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CVF857 will be powered down when
the CLK,CLK stop running.
2. AV
DD
Nominal is 2.5V for PC1600, PC2100, and PC2700. AV
DD
Nominal is 2.6V for PC3200.
Z = High impedance
X = Don’t care
08-0298
3
PS8683D
10/06/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Absolute Maximum Ratings
(Over operating free-air temperature range)
Symbol
V
DDQ
, AV
DD
V
I
V
O
I
IK
I
OK
I
O
I
O(PWR)
Tstg
∅
JA
∅
JC
Parame te r
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Output voltage range
Input Clamp Current
Output Clamp Current
Continuous output Current
Continuous current through each AV
DD
, V
DDQ
, or GND
Storage temperature
Junction to ambient thermal (package A)
Junction to case thermal (package A)
M in.
– 0.5
– 0.5
– 0.5
– 50
– 50
– 50
– 100
– 65
M a x.
3.6
V
DDQ
+0.5
50
50
50
100
150
104
38
o
o
o
C
Units
V
mA
C/w
C/w
Note:
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Specifications
Recommended Operating Conditions
Symbol
AV
DD
V
DDQ
V
IL
V
IH
I
OH
I
OL
V
IX
V
IN
V
ID
T
A
Analog/core supply voltage
Output supply voltage
Low- level input voltage for PWRDWN pin
High- level input voltage for PWRDWN pin
High- level output current
Low- level output current
Input differential- pair crossing voltage
Input voltage level
Input differential voltage between CLK and
CLK
O perating free air temperature
DC
AC
P C 16 0 0 - P C 2 7 0 0
P C 3200
Parame te r
M in.
V
DDQ
– 0.12
2 .3
2 .5
–0.3
1. 7
–
–
(V
DDQ
/2)
–0.2
–0.3
0.36
0 .7
–40
Nom.
V
DDQ
2.5
2.6
M a x.
2.7
2. 7
2. 7
0.7
V
DDQ
+0.3
12
–12
(V
DDQ
/2) +0.2
V
DDQ
+0.3
V
DDQ
+0.6
V
DDQ
+0.6
85
°C
V
mA
V
Units
08-0298
4
PS8683D
10/06/08
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
Timing Requirements for PC1600 ~ PC2700
(Over recommended operating free-air temperature)
Symbol
De s cription
Operating clock frequency
(1,2)
Application clock frequency
(3)
Input clock duty cycle
PLL stabilization time after powerup
AV
DD
, V
DDQ
= 2.5V ±0.2V
M in.
f
CK
t
DC
t
STAB
60
95
40
M a x.
170
17 0
60
100
MHz
%
μ
s
Units
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing
parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
Electrical Characteristics for PC1600 ~ PC2700
(Over recommended operating free-air temperature)
Parame te r
V
IK
V
OH
All inputs
High output voltage
Te s t Conditions
I
I
= –18mA
I
OH
= –100
μ
A
I
OH
= –12mA
I
OL
= 100
μ
A
I
OL
= 12mA
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
CLK & CLK = 0 MHz,
PWRDWN = Low
CLK & CLK = 170 MHz
All outputs are open
CLK & CLK = 170 MHz
V
I
= V
DDQ
or GND
2.7V
2 . 7V
2.5V
2.0
A
VDD
, V
DDQ
2.3V
2.3 to 2.7V
2.3V
2.3 to 2.7V
2.3V
2.7V
2.7V
V
DDQ
– 0.1
1.7
0. 1
0.6
±10
μ
A
200
300
12
3 .5
pF
V
I
= V
DDQ
or GND
2.5V
–0.25
0.25
mA
mA
V
M in.
Typ.
M ax.
–1.2
Units
V
OL
Low output voltage
CLK, FBIN
PWRDWN
Static supply current I
DDQ
+ I
ADD
Dynamic supply current of V
DDQ
Dynamic supply current of AV
DD
CLK and CLK
FBIN and FBIN
CLK and CLK
(5)
FBIN and
FBIN
(5)
I
I
I
DDPD
I
DDQ
I
ADD
C
I
C
I(
Δ)
Note:
4. The maximum power-down clock frequency is below 20 MHz.
5. Guaranteed by design, but not production tested.
08-0298
5
PS8683D
10/06/08
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