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IDT74FCT807CTPYG

Description
FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
Categorysemiconductor    logic   
File Size79KB,8 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT74FCT807CTPYG Overview

FCT SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20

IDT74FCT807CTPYG Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage5.25 V
Minimum supply/operating voltage4.75 V
Rated supply voltage5 V
Processing package descriptionSOIC-20
stateDISCONTINUED
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingtin lead
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
seriesFCT
Enter conditionsSCHMITT trigger
Logic IC typeLow Skew Clock Driver
Number of inverted outputs0.0
Real output number10
propagation delay TPD3.8 ns
Maximum same-side bending0.5000 ns
Max-Min frequency100 MHz
IDT74FCT807BT/CT
FAST CMOS 1-TO-10 CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
1-TO-10 CLOCK DRIVER
IDT74FCT807BT/CT
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew < 250ps (max.)
Very low duty cycle distortion < 350ps (max.)
High speed: propagation delay < 2.5ns (max.)
100MHz operation
TTL compatible inputs and outputs
TTL level output voltage swings
1:10 fanout
Output rise and fall time < 1.5ns (max)
Low input capacitance: 4.5pF typical
High drive: -32mA I
OH
, +48mA I
OL
Available in QSOP, SSOP, and SOIC packages
DESCRIPTION:
The FCT807T clock driver is built using advanced dual metal CMOS
technology. This low skew clock driver features 1:10 fanout, providing
minimal loading on the preceding drivers. The FCT807T offers low
capacitance inputs with hysteresis for improved noise margins. TTL level
outputs and multiple power and grounds reduce noise. The device also
features -32/48mA drive capability for driving low impedance traces.
FUNCTIONAL BLOCK DIAGRAM
O
1
PIN CONFIGURATION
IN
O
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
10
O
9
GND
O
8
V
CC
O
7
GND
O
6
O
5
GND
O
1
O
3
V
CC
O
2
O
4
GND
O
3
O
5
V
CC
IN
O
4
O
6
GND
O
7
O
8
QSOP/ SOIC/ SSOP
TOP VIEW
O
9
O
10
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2006
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 2010
DSC-4242/4

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