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IDT74FCT543DTSOG

Description
FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
Categorysemiconductor    logic   
File Size73KB,7 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT74FCT543DTSOG Overview

FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24

IDT74FCT543DTSOG Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals24
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage5.25 V
Minimum supply/operating voltage4.75 V
Rated supply voltage5 V
Number of ports2
Processing package descriptionGREEN, MS-013-AD, SOIC-24
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE TIN
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
seriesFCT
Output characteristics3-ST
Logic IC typeREGISTERED TRANSCEIVER
Number of digits8
Output polarityTRUE
propagation delay TPD8 ns
IDT74FCT543AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
FEATURES:
A, C, and D grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
IDT74FCT543AT/CT/DT
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A
0
–A
7
or to take data from B
0
–B
7
, as indicated in the
Function Table. With
CEAB
low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the
LEAB
signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With
CEAB
and
OEAB
both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA
and
OEBA
inputs.
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
D
LE
A
0
Q
D
LE
Q
B
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DETAIL A x 7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JUNE 2006
DSC-5489/6
© 2006 Integrated Device Technology, Inc.
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