FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 843002-01 is a 2 output LVPECL synthesizer optimized
to generate Ethernet reference clock frequencies. Using a
25MHz 18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins
(F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The 843002-
01 uses ICS’ 3
rd
generation low phase noise VCO technology
and can achieve 1ps or lower typical rms phase jitter, easily
meeting Ethernet jitter requirements. The 843002-01 is
packaged in a small 20-pin TSSOP package.
843002-01
DATASHEET
F
EATURES
• Two 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies:
156.25MHz, 125MHz and 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.54ps (typical)
• Typical phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ................-97.3 dBc/Hz
1KHz ..............-119.1 dBc/Hz
10KHz ..............-126.4 dBc/Hz
100KHz ..............-127.6 dBc/Hz
• Full 3.3V supply mode
• Lead-Free package fully RoHS compliant
• -30°C to 85°C ambient operating temperature
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Divider
Value
25
25
25
Not Used
N Divider
Value
4
5
10
Output Frequency
(25MHz Ref.)
156.25
125
62.5
Not Used
P
IN
A
SSIGNMENT
nc
V
CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CCO
Q1
nQ1
V
EE
V
CC
nXTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
F_SEL1
B
LOCK
D
IAGRAM
F_SEL[1:0]
nPLL_SEL
Pulldown
Pulldown
843002-01
2
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1
not used
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
Q0
G Package
Top View
nQO
TEST_CLK
Pulldown
1
1
Q1
nQ1
25MHz
XTAL_IN
XTAL_OUT
nXTAL_SEL
Pulldown
OSC
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
0
M = 25 (fixed)
MR
Pulldown
843002-01 REVISION B 4/6/15
1
©2015 Integrated Device Technology, Inc.
843002-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
CCO
Q0, nQ0
MR
Unused
Power
Ouput
Input
Type
Description
No connect.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are en-
abled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Output supply pins.
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
2, 20
Pulldown
nPLL_SEL
V
CCA
F_SEL0,
F_SEL1
V
CC
XTAL_OUT,
XTAL_IN
TEST_CLK
nXTAL_SEL
V
EE
nQ1, Q1
V
CCO
Input
Power
Input
Power
Input
Input
Input
Power
Output
Power
NOTE: refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
2
REVISION B 4/6/15
843002-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
3.63
3.63
135
100
15
31
Units
V
V
V
mA
mA
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
nPLL_SEL, nXTAL_SEL,
Input
F_SEL0, F_SEL1, MR
Low Voltage
TEST_CLK
Input
High Current
Input
Low Current
TEST_CLK, MR, nPLL_
SEL, nXTAL_SEL
TEST_CLK, MR, nPLL_
SEL, nXTAL_SEL
V
CC
= V
IN
= 3.63V
V
CC
= 3.63V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V + 0.3
CC
Units
V
V
V
µA
µA
0.8
1.0
150
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Ω
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
- 2V.
REVISION B 4/6/15
3
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
843002-01 DATA SHEET
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
22.4
Test Conditions
Minimum
Typical Maximum
25
27.2
50
7
Units
MHz
Ω
pF
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, TA = -30°C
TO
85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter; NOTE 3
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
300
0.54
0.60
0.79
600
51
Test Conditions
F_SEL[1,:0] = 00
F_SEL[1,:0] = 01
F_SEL[1,:0] = 10
Minimum
140
112
56
Typical
Maximum
170
136
68
20
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
49
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CCO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Phase jitter is dependent on the input source used.
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
4
REVISION B 4/6/15
843002-01 DATA SHEET
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
T
YPICAL
P
HASE
N
OISE AT
62.5MH
Z
10 Gigabit Ethernet Filter
62.5MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.79ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
-180
-190
100
1k
10k
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
10 Gigabit Ethernet Filter
125MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.60ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
-190
100
1k
10k
O
FFSET
F
REQUENCY
(H
Z
)
REVISION B 4/6/15
5
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
➤
-170
-180
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
100k
1M
10M
100M
➤
➤
-170
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
100k
1M
10M
100M
➤
➤
➤
Embedded System
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