IXYS
Features:
IXS839 / IXS839A / IXS839B
Synchronous Buck MOSFET Driver
General Description
The IXS839/IXS839A/IXS839B are 2A Source / 4A
Sink Synchronous Buck MOSFET Drivers. These
Synchronous Buck MOSFET Drivers are specifically
designed to drive two N-channel power MOSFETs
in a synchronous buck converter. The High-Side
driver is powered via a bootstrapped power
connection. The driver is capable of 20ns High-Side
output, and 18ns Low-Side output transition times
driving a 3000pF load.
The IXS839 and IXS839B incorporate an
undervoltage lockout to prevent unintentional gate
drive output during low voltage conditions. The
IXS83A/B include External Shutdown and Low-Side
Drive Shutdown features. Simultaneous shutdown
of both outputs prevents rapid output capacitor
discharge. The high-side turn-on delay is adjustable
with an external capacitor added at the DLY pin.
The IXS839/839A/839B are designed to operate
over a temperature range of -40°C to +85°C. The
IXS839 is available in an 8-Lead SOIC, the
IXS839A and the IXS839B in a 10-pin QFN.
•
Logic Level Gate Drive Compatible
•
2A Source, 4A Sink Peak Drive Current
•
Programmable High-Side Driver Turn-on Delay
•
Supports Floating Voltage for Top Driver Up to
24V
•
IXS839/839B: Undervoltage Lockout
•
IXS839A/B: Output Shutdown, Low Side
Shutdown Inputs
•
10µA Shut Down Current
•
2mA Quiescent Current (Non- Switching)
•
Bootstrapped High Side Driver
•
Cross-Conduction Protection
Applications:
•
Multiphase Desktop CPU Supplies
•
Mobile CPU Core Voltage supplies
•
High Current / Low Voltage DC/DC
Synchronous Buck Converters
Figure 1. IXS839 Functional Block Diagram
and General Application Circuit
5V
VIN
Figure 2. IXS839A Functional Block Diagram
and General Application Circuit
5V
VIN
VDD
4
UVLO
VDD
8
DBST
DBST
1
BST
3
2
4
OVERLAP
BST
8
PWM
HGD
Q1
SD
HGD
Q1
2
OVERLAP
PROTECTION
CIRCUIT
7
SW
CBST
VOUT
PWM
5
DLY
PROTECTION
CIRCUIT
1
SW
CBST
VOUT
DLY
3
5
LGD
Q2
7
9
LGD
Q2
CDLY
PGND
CDLY
6
10
LSD
PGND
6
Copyright © IXYS CORPORATION 2004
IXYS
5V
VIN
IXS839 / IXS839A / IXS839B
Figure 3. IXS839B Functional Block Diagram and General Application Circuit
5
UVLO
VDD
DBST
10
9
1
OVERLAP
PWM
PROTECTION
CIRCUIT
DLY
BST
SD
HGD
Q1
2
8
SW
CBST
VOUT
4
6
LGD
Q2
CDLY
7
LSD
PGND
3
Ordering Information
Part No.
IXS839S1
IXS839S1T/R
IXS839AQ2
IXS839AQ2T/R
IXS839BQ2
IXS839BQ2T/R
Description
Under Voltage Lockout
Under Voltage Lockout
Driver Shutdown, Low Side Shutdown
Driver Shutdown, Low Side Shutdown
Under Voltage Lockout , Driver Shutdown, Low Side Shutdown
Under Voltage Lockout , Driver Shutdown, Low Side Shutdown
Package
8-Pin SOIC
8-Pin SOIC
10-Pin QFN
10-Pin QFN
10-Pin QFN
10-Pin QFN
Pack Quantity
98 (Tube)
2500 (Tape & Reel)
121 (Tube)
2000 (Tape & Reel)
121 (Tube)
2000 (Tape & Reel)
Absolute Maximum Ratings
Parameter
V
DD
BST
BST to SW
SW
PWM
Operating Ambient Temp Range
Operating Junction Temp Range
θJA
θJC
Storage Temp Range
Lead Temperature (Soldering, 10 sec)
Rating
-0.3V to +7V
-0.3V to +30V
-0.3V to +7V
-0.2V to +24V
-0.3V to +7V
-40°C to +85°C
-40°C to +125°C
150°C/W
40°C/W
-65°C to +150°C
+300°C
Absolute Maximum Ratings are stress ratings.
Stresses in excess of these ratings can cause
permanent damage to the device. Functional
operation of the device at these or any other
conditions beyond those indicated in the operational
sections of this data sheet is not implied. Exposure
of the device to the absolute maximum ratings for
an extended period may degrade the device and
affect its reliability.
ESD Warning
ESD (electrostatic discharge) sensitive device. Electrostatic charges can readily accumulate on test equipment and the human body
in excess of 4000 Volts. This energy can discharge without detection. Although the IXS839/839A/839B feature proprietary ESD
protection circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
2
IXYS
Pin Description and Configurations
IXS839
1
2
3
IXS839A
3
5
7
IXS839B
10
2
4
Name
BST
PWM
DLY
Description
IXS839 / IXS839A / IXS839B
4
5
6
7
8
N/A
N/A
8
9
10
1
2
4
6
5
6
7
8
9
1
3
VDD
LGD
PGND
SW
HGD
__
SD
___
LSD
Upper Gate Driver Floating DC Power Terminal for Bootstrap
Capacitor Connection.
TTL-level Input Signal with active pull-down. PWM input to the
Gate Drivers.
Terminal for External Delay Capacitor Connection. Capacitor
to Ground at this pin adds propagation delay from Lower Gate
Driver going Low to the Upper Gate Driver going High.
t
DLY
(nS) = C
DLY
(pF) x (0.5nS/pF)
Positive Supply Terminal for Logic and Lower Gate Driver. A
ceramic bypass capacitor of 1uF should be connected from
VDD to PGND.
Lower Gate Driver Output Terminal
Lower Gate Driver DC Power Return Terminal, Logic and
Analog Ground
Upper Gate Driver Floating DC Power Return Terminal
Upper Gate Driver Output Terminal
TTL-level Shut Down Input Signal with active pull-up.
SD
enables normal operation when high. When
SD
is low,
the driver outputs are forced low and I
DD
is at its minimum.
TTL-level Low Side Shut Down Input Signal with active pull-
up.
LSD,
when low forces the Lower Gate Driver output low.
When
LSD
is high, the lower Gate Driver output is enabled.
SOIC and QFN Top View Pin Configurations
BST 1
PWM 2
DLY 3
VDD 4
IXS839S1
8 HGD
7 SW
6 PGND
5 LGD
SW 1
HGD 2
BST 3
SD
4
10 PGND
IXS839AQ2 9
8
7
6
LGD
VDD
DLY
LSD
SD 1
PWM
2
10 BST
IXS839BQ2 9
8
7
6
HGD
SW
PGND
LGD
LSD 3
DLY 4
VDD 5
PWM 5
3
IXYS
Electrical Characteristics
Power Supply Terminals
Parameter
Symbol
Analog Supply
Voltage Range
High Gate Driver
Supply Voltage Range
Low Gate Driver
Supply Voltage Range
Floating Supply
Voltage Range
Analog Supply
Current
High Gate Driver
Supply Current
Analog Supply
Current
High Gate Driver
Supply Current
V
DD
V
DD
V
BST -
V
SW
V
DD -
V
PGND
V
SW -
V
PGDN
I
DD
I
BST
I
DD_Shutdown
I
BST_Shutdown
Normal Mode
PWM = V
PGND
Normal Mode
PWM = V
PGND
SD
= PWM = V
PGND
IXS839 / IXS839A / IXS839B
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Conditions
Min
4.5
4.5
4.5
0.0
Typ
Max
5.5
5.5
5.5
24.0
Unit
V
V
V
V
mA
mA
µA
2
IXS839/839B
IXS839A
IXS839/839B
IXS839A
0.5
10
50
<1
4
1
1.5
Shut Down Mode,
LSD
= V
DD
,
Shut Down Mode
LSD
= PWM = V
PGND
10
µA
Digital Input Terminals
Parameter
Input Leakage Current
Input pull-down Current
Input pull-up Current
Input pull-up Current
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Symbol
I
IN
Conditions
PWM = V
PGND
LSD = SD = V
DD
PWM = V
DD
__
SD = V
PGND
___
LSD = V
PGND
Min
-1
2
-2
-2
2.0
Typ
Max
1
Unit
µA
µA
µA
µA
V
10
-10
-10
100
-100
-100
V
IH
V
IL
0.8
V
UVLO Circuit
Parameter
V
DD
Rising Threshold
V
DD
Falling Threshold
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Symbol
UVOL
RISE
UVOL
FALL
Conditions
Min
4.2
3.9
Typ
4.4
4.25
Max
4.5
4.5
Unit
V
V
Delay Circuit
Parameter
Upper Gate-Driver Turn
on Delay Time with
respect to external delay
capacitor
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Symbol
t
DLY
Conditions
Capacitor C
DLY
(pF) from DLY
pin to PGND
Min
Typ
0.5
Max
Unit
nS/pF
4
IXYS
Electrical Characteristics
High Side Gate Driver Circuit
Parameter
Symbol
High Side Gate-Driver
On-Resistance, Sourcing
Current
High Side Gate-Driver
On-Resistance, Sinking
Current
High Side Gate-Driver
(1)
Rise-Time
High Side Gate-Driver
(1)
Fall-Time
Propagation Delay
(1)
R
HGD_SRC
IXS839 / IXS839A / IXS839B
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Conditions
V
BST
– V
SW
= 4.6V
Min
Typ
Max
2.2
Unit
Ω
R
HGD_SNK
V
BST
– V
SW
= 4.6V
C
LOAD
= 3nF
T
R_HGD
measured from 10% to
90% of (V
HGD
- V
SW
)
C
LOAD
= 3nF
T
F_HGD
measured from 90% to
10% of (V
HGD
- V
SW
)
C
LOAD_HGD
= C
LOAD_LGD
= 3nF
C
DLY
= 0pF
1.2
Ω
t
R_HGD
20
nS
t
F_HGD
t
PD_HGD1
t
PD_HGD2
15
35
50
nS
nS
nS
Low Side Gate Driver Circuit
Parameter
Symbol
Low Side Gate-Driver
On-Resistance, Sourcing
Current
Low Side Gate-Driver
On-Resistance, Sinking
Current
Low Side Gate-Driver
(1)
Rise-Time
Low Side Gate-Driver
(1)
Fall-Time
Propagation Delay
(1)
R
LGD_SRC
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Conditions
V
DD
– V
PGND
= 4.6V
Min
Typ
Max
2
Unit
Ω
R
LGD_SNK
V
DD
– V
PGND
= 4.6V
C
LOAD
= 3nF
T
R_LGD
measured from 10% to
90% of (V
LGD
– V
PGND
)
C
LOAD
= 3nF
T
F_LGD
measured from 90% to
10% of (V
LGD
- V
SW
)
C
LOAD_HGD
= C
LOAD_LGD
= 3nF
C
DLY
= 0pF
1
Ω
t
R_LGD
18
nS
t
F_LGD
t
PD_LGD1
t
PD_LGD2
12
60
20
nS
nS
nS
Shut Down Circuit Characteristics
Parameter
Symbol
Propagation Delay
Propagation Delay
(2)
Propagation Delay
(3)
Propagation Delay
(3)
(2)
T
A
= -40°C to 85°C, V
DD
= 5V, 4V < V
BST
< 26V
Conditions
Min
Typ
25
10
400
800
Max
50
20
800
1200
Unit
nS
nS
nS
nS
t
PD_LGDSD1
t
PD_LGDSD2
t
PD_GDSD1
t
PD_GDSD2
*Notes:
(1) See Timing Diagram in Figure 4
(2) See Timing Diagram in Figure 5
(3) See Timing Diagram in Figure 6
5
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