EEWORLDEEWORLDEEWORLD

Part Number

Search

70V3569S4DR

Description
SRAM 16K X 36 SYNCH DPRAM
Categorystorage    storage   
File Size193KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

70V3569S4DR Online Shopping

Suppliers Part Number Price MOQ In stock  
70V3569S4DR - - View Buy Now

70V3569S4DR Overview

SRAM 16K X 36 SYNCH DPRAM

70V3569S4DR Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePQFP
package instructionQFP, QFP208,1.2SQ,20
Contacts208
Manufacturer packaging codeDR208
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.B
Maximum access time4.2 ns
Other featuresPIPELINED OUTPUT MODE, SELF TIMED WRITE CYCLE
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeS-PQFP-G208
JESD-609 codee0
memory density589824 bit
Memory IC TypeDUAL-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals208
word count16384 words
character code16000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.46 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
IDT70V3569S
HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts availble, see ordering instructions
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B B
WW
0 1
L L
B B
WW
2 3
L L
B BB B
W WW W
3 2 1 0
R RR R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
16K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
13L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
13R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4831 tbl 01
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC 4831/14
PCB
Dear experts!! What are the commonly used units for PCB production? What should we pay attention to when making it?...
新手为学习 PCB Design
[Samples] +Ti is very efficient
This time, I applied for 3 samples: INA300AIDSQT, ATL431AQDBZR, MSP430FR4133IPMR. Order date: 8/5/2015 8:56 PM, sample received date: 8/7/2015. From review to delivery to receipt, it took exactly 48 h...
stu_deepblue TI Technology Forum
Has anyone used the following RF?
433MHzRFTransceiver-v1.1...
wang_gdut RF/Wirelessly
Copyright issues regarding reposting
Now, if you search for an article, you often find that you can search for the same article on many different websites. What are the general situations regarding copyright issues? How to prevent or cir...
wangfuchong Talking
DB HiTek Completes Global Shutter and SPAD Technology Development to Further Expand Image Sensors
DB HiTek announced that it has developed a 110nm-based global shutter and single-photon avalanche diode (SPAD) process and will expand its image sensor market. The global shutter senses image informat...
国际文传 Sensor
DXP Modify Board Size
DXP PCB board selection item width and height value modification cannot modify the circuit board size...
hongyuchang PCB Design

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1587  706  2918  2006  2907  32  15  59  41  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号