74LVC841ADB datasheet, PDF - EEWORLD Datasheet

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74LVC841ADB: DescriptionLatches 10BIT BUS INTERFC LATCH 3ST; Categorylogic logic; File Size141KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC841ADB Overview

Latches 10BIT BUS INTERFC LATCH 3ST

74LVC841ADB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SSOP
package instruction	SSOP, SSOP24,.3
Contacts	24
Reach Compliance Code	compliant
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G24
JESD-609 code	e4
length	8.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	10
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP24,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	6.7 ns
propagation delay (tpd)	11 ns
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	5.3 mm
Base Number Matches	1

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74LVC841A

10-bit transparent latch with 5 V tolerant inputs/outputs;

3-state

Rev. 4 — 2 April 2013

Product data sheet

1. General description

The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each

latch and 3-state outputs for bus applications. A latch enable (pin LE) input and an output

enable (pin OE) input are common to all internal latches. The device consists of ten

transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs

enters the latches. In this condition, the latches are transparent, that is, a latch output

changes each time its corresponding D-input changes. When pin LE is LOW, the latches

store the information that was present at the D-inputs a set-up time preceding the HIGH to

LOW transition of pin LE.

When pin OE is LOW, the contents of the ten latches are available at the outputs. When

pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the pin OE

input does not affect the state of the latches.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices as translators in

mixed 3.3 V and 5 V applications.

2. Features and benefits



5 V tolerant inputs/outputs; for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Flow-through pinout architecture

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C.

74LVC841ADB Related Products

	74LVC841ADB	74LVC841AD118	74LVC841ADB118	74LVC841APW-T	74LVC841AD,112	74LVC841ABQ,118
Description	Latches 10BIT BUS INTERFC LATCH 3ST	Latches 10BIT BUS INTERFC	Latches 10BIT BUS INTERFC	Latches 10BIT BUS INTERFC LATCH 3ST	Locking 10BIT BUS INTERFC	Latch Transpar 3-ST 10-CH D-Type 24-Pin
Is it Rohs certified?	conform to	-	-	conform to	conform to	conform to
Maker	NXP	-	-	NXP	NXP	NXP
Parts packaging code	SSOP	-	-	TSSOP	SOP	QFN
package instruction	SSOP, SSOP24,.3	-	-	TSSOP,	7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24	3.50 X 5.50 MM, 0.85 MM HEIGHT, PLASTIC, SOT-815-1, DHVQFN-24
Contacts	24	-	-	24	24	24
Reach Compliance Code	compliant	-	-	unknown	compliant	compliant
series	LVC/LCX/Z	-	-	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G24	-	-	R-PDSO-G24	R-PDSO-G24	R-PQCC-N24
JESD-609 code	e4	-	-	e4	e4	e4
length	8.2 mm	-	-	7.8 mm	15.4 mm	5.5 mm
Load capacitance (CL)	50 pF	-	-	50 pF	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	-	-	BUS DRIVER	BUS DRIVER	BUS DRIVER
Humidity sensitivity level	1	-	-	1	1	1
Number of digits	10	-	-	10	10	10
Number of functions	1	-	-	1	1	1
Number of ports	2	-	-	2	2	2
Number of terminals	24	-	-	24	24	24
Maximum operating temperature	125 °C	-	-	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-	-	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	-	-	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	-	-	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	-	-	TSSOP	SOP	HVQCCN
Package shape	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	-	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	-	-	260	260	260
propagation delay (tpd)	11 ns	-	-	11 ns	11 ns	11 ns
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2 mm	-	-	1.1 mm	2.65 mm	1 mm
Maximum supply voltage (Vsup)	3.6 V	-	-	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	-	-	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.7 V	-	-	2.7 V	2.7 V	2.7 V
surface mount	YES	-	-	YES	YES	YES
technology	CMOS	-	-	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	-	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD	-	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	-	-	GULL WING	GULL WING	NO LEAD
Terminal pitch	0.65 mm	-	-	0.65 mm	1.27 mm	0.5 mm
Terminal location	DUAL	-	-	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	30	-	-	30	30	30
width	5.3 mm	-	-	4.4 mm	7.5 mm	3.5 mm
Base Number Matches	1	-	-	1	1	1

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