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5P49V5901A034NLGI8

Description
Clock Generators & Support Products VERSACLOCK 5
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size437KB,37 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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5P49V5901A034NLGI8 Overview

Clock Generators & Support Products VERSACLOCK 5

5P49V5901A034NLGI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Reach Compliance Codecompliant
ECCN codeEAR99
JESD-30 codeS-PQCC-N24
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCN
Encapsulate equivalent codeLCC24,.16SQ,20
Package shapeSQUARE
Package formCHIP CARRIER
power supply1.8/3.3 V
Certification statusNot Qualified
Maximum slew rate47 mA
surface mountYES
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Programmable Clock Generator
5P49V5901
DATASHEET
Description
The 5P49V5901 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Features
Generates up to four independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
One reference LVCMOS output clock
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Pin Assignment
OUT0_SEL_I2CB
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
OUT1B
V
DDO
0
V
DDO
1
OUT1
V
DDD
Output frequency ranges:
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
CLKIN
CLKINB
XOUT
XIN/REF
V
DDA
CLKSEL
24 23 22 21 20 19
1
18
2
3
4
5
6
7
8
9
17
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
EPAD
16
15
14
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
13
10 11 12
24-pin VFQFPN
1
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
©2017 Integrated Device Technology, Inc.
SEL1/SDA
SEL0/SCL
SD/OE
V
DDO
4
OUT4
5P49V5901 MARCH 3, 2017
OUT4B
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