8W, Qi-compliant, Wireless Power Transmitter
with Integrated Full Bridge Inverter
Features
•
4.5V to 6.9V input operating voltage range, supporting:
•
USB or AC adapter
•
USB dedicated charger port (DCP) detection
•
WPC-1.2.2 compliant for A5 or A11-type coils
•
Integrated, high-efficiency power stage with low R
DS(ON)
•
Integrated foreign object detection & current sense
•
Excellent EMI performance eliminates need for EMI filter
•
Supports up to 8W power transfer to the receiver
•
Demodulates and Decodes Communication Packets from
•
•
•
•
•
•
•
•
•
•
•
WPC-compliant Receivers
I
2
C Interface for EEPROM access
Programmable input over-voltage protection
Programmable soft start
Current limit and over-temperature protection
-40° to +85°C temperature range
7 x 7 mm 56-VFQFPN package
P9038
DATASHEET
Description
The P9038 is a WPC-compliant Wireless Power Transmitter
for A5 and A11 designs operating from 5V supplies
conforming with WPC Specification 1.2.2. Operating in the
WPC-compliant mode, the integrated full-bridge inverter
supports 8W power transfer utilizing the P902x Receiver
family, and ensures efficient switching with EMI/RFI emissions
that are better than the requirements of the WPC
specification.
To safeguard the device and the system under fault
conditions, the P9038 offers resistor programmable Foreign
Object Detection, built-in Over-Current protection, and
programmable Over-Voltage / Over-Temperature protection.
This transmitter is extremely easy to use and provides a
complete WPC-compliant solution with minimum external
parts count, requiring significantly less board space and lower
total solution cost than competing products.
The P9038 is available in a compact 7 x 7 mm VFQFPN
package, and it is rated for -40° to +85°C temperature range.
Applications
Furniture
PC peripherals
Rugged electronic gear
Small appliances
Battery-powered electronics
Typical Application Circuit
EN
C
IN
IN
ISNSN_IN
EN
P9038
BST2
SW2
C
BST2
C
SW2
VO
C
OUT
L
CTX
R
FILT_N
R
SNS
C
FILT_CM
R
FILT_P
C
FILT_N
C
FILT_P
ISNSP_IN
SW1
BST1
C
BST1
Z1
C
SW1
REG_IN
C
IN
GPIO_1
Z2
GATE
R
GATE
ADAPTOR
DP
DM
LDO5V
C
LDO5V
EEPROM
A0
A1
A2
VSS
VCC
WP
SCL
SDA
RESET
C
GATE
VBUS_SNS
DP
DM
LDO5V
LDO2P5V_IN
INV5V_IN
OVP_SEL
SCL
SDA
ISNS
C
HPF
HPF
SHIELD1
SHIELD2
ISNS_AVG
VSNS_AVG
C
VSNS_AVG
LDO2P5V
C
LDO2P5V
LDO2P5V
C
ISNS_1
R
SHLD
=10MO
C
ISNS_AVG
GPIO_0 - GPIO_6
WP
RESET
GND
GPIO_6
P9038 August 1, 2016
1
©2016 Integrated Device Technology, Inc.
P9038 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below (Table
1
and
Table 2)
can cause permanent damage to the P9038. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Table 1: Absolute Maximum Ratings Summary.
(All voltages are referred to ground.)
Pins
VBUS_SNS
EN, IN, REG_IN, SW1, SW2, ISNSN_IN, ISNSP_IN
GPIO_6:0, SCL, SDA, RESET, DP, DM, NC, NC1, NC2, NC3, SHIELD2, LDO5V, LDO2P5V_IN,
INV5V_IN, VFOD_SNS, ISNS, HPF, OVP_SEL, ISNS_V
BST1, BST2
GATE
GND, REFGND, PGND1, PGND2
SHIELD1
LDO2P5V
Rating
-0.3 to 27
-0.3 to 12.5
-0.3 to 5.5
-0.3 to SW+6
-0.3 to REG_IN+6
+0.3
-0.3 to 8
-0.3 to 2.75
Units
V
V
V
V
V
V
V
V
Table 2: Package Thermal Information
1,2,3
Symbol
Θ
JA
Θ
JC
Θ
JB
T
J
T
A
T
STG
T
LEAD
Description
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Thermal Resistance Junction to Board
Operating Junction Temperature
Ambient Operating Temperature
Storage Temperature
Lead Temperature (soldering, 10s)
Rating (VFQFPN)
25.5
8.6
2.4
-40 to +125
-40 to +85
-55 to +150
+300
Units
C/W
C/W
C/W
C
C
C
C
NOTES:
1. The maximum power dissipation is P
D(MAX)
= (T
J(MAX
) - T
A
) /
Θ
JA
where T
J(MAX)
is 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature,
and the device will enter thermal shutdown.
2. This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 3" x 4.5" in still air conditions.
3. Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables.
Table 3: ESD Information
Test Model
HBM
CDM
Pins
All pins
All pins
Ratings
±2000
±500
Units
V
V
©2016 Integrated Device Technology, Inc.
2
P9038 August 1, 2016
P9038 DATASHEET
Electrical Specifications Table
Table 4: Device Characteristics
V
IN
= 5V, EN = 0V, C
IN
= 40μF, Coil = A11, C
S
= 400nF, T
A
= -40° to +85°C, unless otherwise noted. Typical values are at 25°C.
Symbol
Description
Conditions
Min
Typ
Max
Units
Input Supplies & UVLO
V
BUS
Input Operating Range
Standby Input Current
(no ping)
I
IN_REGIN2
Standby Input Current
(pinging)
Sleep Mode
Input Current
I
IN_VBUS_SNS
VBUS_SNS
Input Current
REGIN Under-Voltage
Protection Trip Points
VBUS_MIN to OVP_Max
After power-up sequence complete.
No coil, no switching at SW1, SW2,
LDO5V, LDO2P5V. REG_IN = 6.9V
After power-up sequence complete.
Average including pinging.
EN= REG_IN = 6.9V
VBUS_SNS = 6.9V
Rising
V
REGIN_UVLO
Falling
Hysteresis
Full Bridge PWM Generators
F
SW
F
SW
LSB
Duty
4
Switching Frequency
Switching Frequency
Step Size
Duty Cycle
Over-Current Protection
Trip Point Range
Over-Current Protection
Trip Point Accuracy
V
REG
= 4.5V-6.9V
V
IN
= 5V, cycle-by-cycle protection,
programmable range
V
IN
= 5V, OCP Setting = 5A
10
110
12.5
50
90
205
kHz
ns
%
3.4
150
4.5
8
15
600
1
4.1
6.9
12
V
mA
mA
uA
mA
V
V
mV
Full Bridge Inverter
I
HS_OCP_RNG
I
HS_OCP_ACC
3
-20
15
20
A
%
Input OVP, Inrush Control, and Current Limit
V
BUS
rising, OVP_SEL pin grounded
V
BUS_OVP
V
BUS
Over-Voltage
Protection Trip Point
V
BUS
rising, OVP_SEL pin 220k 5% to
GND
V
BUS
rising, OVP_SEL pin floating
Hysteresis
V
REG_OVP
T
GATE_RISE
D
GATE_FALL
I
GATE_LKG
REG_IN Over-Voltage
Protection Trip Point
GATE Voltage Rise
Time
Delay from input OVP to
GATE Voltage
Pull-down
GATE Leakage
V
REG_IN
rising
V
BUS
= 5V, Gate cap = 4nF
V
GATE
= 1V to V
IN
+4V
V
GATE
Pull down Time, Gate cap = 4nF
V
GATE
= V
IN
+4V to V
IN
VBUS_SNS = 0V, REG_IN = 5V,
V
GATE
= 10V
-1
6.7
5.8
7.3
200
9.3
3.6
400
+1
9.8
7.15
6.3
7.85
V
V
V
mV
V
ms
ns
µA
Input Average Current Sense
P9038 August 1, 2016
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©2016 Integrated Device Technology, Inc.
P9038 DATASHEET
Symbol
ISEN
IR
ISEN
ACC
LDO2P5V
3
V
IN
V
OUT
I
OUT_MAX
LDO5V
3
V
IN
V
OUT
I
OUT_MAX
Description
Input Range
Current Sense
Accuracy
V
IN
V
OUT
I
OUT_MAX
Input Voltage
Output Voltage
Maximum
Output Current
Conditions
ISNSP_IN, ISNSN_IN
V
REGIN
= 4.5 to 7.2V, I
SENSR
= 1.5A,
Note 1
V
IN
V
OUT
I
OUT_MAX
Min
REGIN
-0.3V
Typ
-
+/- 3
Max
REGIN
+0.15V
Units
V
%
V
IN
V
OUT
I
OUT_MAX
4.5
V
IN
V
OUT
I
OUT_MAX
V
IN
V
OUT
I
OUT_MAX
6.9
V
IN
V
OUT
I
OUT_MAX
V
V
I
LOAD
= 10mA, REG_IN = 5.5
5
10
mA
Thermal Shutdown
T
SD
EN
V
IH
V
IL
I
EN
V
IH
V
IL
I
LKG
V
OH
V
OL
RESET
V
IH
V
IL
I
LKG
Input Threshold High
Input Threshold Low
Input Leakage
DP and DM Voltage
Source
V
DP_SRC
V
DM_SRC
DP and DM
Voltage Source Output
Source Current
DP and DM
Voltage Source Output
Sink Current
IDP_SINK
IDM_SINK
IDP_SRC
VDAT_REF
VDP/DM_LGCHI
Current Sink
Current Source
Data Detect Voltage
Logic High
4
V
DP
or V
DM
between 0.5V and 0.7V
250
-1
3.5
1.5
+1
V
V
µA
EN Input Current
Input Threshold High
Input Threshold Low
Input Leakage
Output Logic High
Output Logic Low
I
OH
= -8mA
I
OL
= 8mA
-1
4
0.5
V
EN
= 6.9V
3.5
1.5
+1
General Purpose Inputs / Outputs (GPIO)
5
V
V
µA
V
V
1.1
0.3
25
V
V
μA
Thermal Shutdown
Threshold Rising
Threshold Falling
140
110
°C
°C
DP/DM CHARGER DETECTION
0.6
V
µA
V
DP
or V
DM
at 2.2V
25
7
0.25
2.0
100
500
175
13
0.4
µA
µA
µA
V
V
©2016 Integrated Device Technology, Inc.
P9038 August 1, 2016
P9038 DATASHEET
Symbol
RDP_DWN
CI
IILK
Description
Pull-down Resistance
Input Capacitance
Input Leakage
Conditions
Min
14.25
Typ
19.5
4.5
4.5
Max
0.8
24.8
5
5
+1
+1
Units
V
k
pF
pF
μA
μA
VDP/DM_LGCLO Logic Low
Dm pin, Switch Open
Dp pin, Switch Open
Dm pin, Switch Open V = 5.0
Dp pin, Switch Open V = 5.0
f
SCL_MSTR1
f
SCL_MSTR2
P9038 as Slave
-1
-1
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR2
f
SCL_MSTR2
0
0.6
I
2
C-bus Devices
10
1.3
0.6
100
SCL, SDA (I
2
C Interface)
f
SCL_MSTR1
f
SCL_MSTR2
f
SCL_SLV
t
HD,STA
t
HD:DAT
t
LOW
t
HIGH
t
SU:STA
f
SCL_MSTR1
f
SCL_MSTR2
Clock Frequency
Hold Time (Repeated)
for START Condition
Data Hold Time
Clock Low Period
Clock High Period
Set-up Time for
Repeated START
Condition
Bus Free Time between
STOP and START
Condition
Capacitive Load for
each Bus Line
SCL, SDA
Input Capacitance
5
Input Threshold Low
Input Threshold High
Input Leakage Current
V = 0V & 5V
Output Logic Low (SDA) I = 2mA
1.4
-1.0
1.0
0.25
5
0.4
f
SCL_MSTR1
f
SCL_MSTR1
f
SCL_MSTR2
f
SCL_MSTR2
400
kHz
µs
ns
µs
µs
ns
1.3
µs
t
BUF
C
B
C
BIN
V
IL
V
IH
I
LKG
V
OL
100
pF
pF
V
V
µA
V
NOTES:
1. 10m 1% or better sense resistor is required to meet the FOD specification
2. This current is the sum of the input currents for REG_IN, IN, ISNSP_IN, ISNSN_IN, and EN_B.
3. 3.For internal use - do not externally load.
4. Guaranteed by Design.
5. Any of the GPIO pins is capable of sourcing 8mA. The GPIO connected to the ADC have a max operating input voltage of 2.4V to prevent saturation of the ADC.
P9038 August 1, 2016
5
©2016 Integrated Device Technology, Inc.
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