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Technical Support ..................................................... 19
Document Number: 001-84771 Rev. *I
Page 3 of 19
CY62168G/CY62168GE MoBL
®
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) pinout
[3]
CY62168G
1
NC
NC
I/O
0
V
SS
V
CC
I/O
3
NC
A
19
2
OE
NC
NC
I/O
1
I/O
2
NC
NC
A
8
3
A
0
A
3
A
5
A
17
A
18
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
1
NC
I/O
5
I/O
6
NC
WE
A
11
6
CE
2
NC
I/O
4
V
CC
V
SS
I/O
7
NC
A
20
A
B
C
D
E
F
G
H
Figure 2. 48-ball VFBGA (6 × 8 × 1 mm) pinout
[3, 4]
CY62168GE
Note
3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
4. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-84771 Rev. *I
Page 4 of 19
CY62168G/CY62168GE MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage to ground potential ...................–0.5 V to 6 V
DC voltage applied to outputs
in High Z state
[5]
.................................. –0.5 V to V
CC
+ 0.5 V
DC input voltage
[5]
.............................. –0.5 V to V
CC
+ 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Latch up current ...................................................... >140 mA
Operating Range
Grade
Industrial
Ambient Temperature
–40
C
to +85
C
V
CC
[6]
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40
C
to 85
C
Parameter
V
OH
Description
Output HIGH
voltage
Test Conditions
45 ns/55 ns
Min
1.4
2.0
2.4
2.4
V
CC
– 0.4
[8]
–
–
–
–
1.4
1.8
2.0
2.2
–0.2
–0.3
–0.3
–0.5
–1.0
–1.0
Typ
[7]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
–
–
–
0.2
0.4
0.4
0.4
V
CC
+ 0.2
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.5
0.4
0.6
0.8
0.8
+1.0
+1.0
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
1.65 V to 2.2 V V
CC
= Min, I
OH
= –0.1 mA
2.2 V to 2.7 V V
CC
= Min, I
OH
= –0.1 mA
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
V
CC
= Min, I
OH
= –1.0 mA
V
CC
= Min, I
OH
= –1.0 mA
V
CC
= Min, I
OH
= –0.1 mA
V
OL
Output LOW
voltage
1.65 V to 2.2 V V
CC
= Min, I
OL
= 0.1 mA
2.2 V to 2.7 V V
CC
= Min, I
OL
= 0.1 mA
2.7 V to 3.6 V
4.5 V to 5.5 V
V
CC
= Min, I
OL
= 2.1 mA
V
CC
= Min, I
OL
= 2.1 mA
–
–
–
–
–
–
GND < V
IN
< V
CC
GND < V
OUT
< V
CC
, Output disabled
V
IH
Input HIGH
voltage
1.65 V to 2.2 V –
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
V
IL
Input LOW
voltage
[9]
1.65 V to 2.2 V –
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
I
IX
I
OZ
Input leakage current
Output leakage current
Notes
5. V
IL(min)
= –2.0 V and V
IH(max)
= V
CC
+ 2 V for pulse durations of less than 20 ns.
6. Full Device AC operation assumes a 100 µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for V
CC
range of 1.65 V–2.2 V), V
CC
= 3 V
(for V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
8. This parameter is guaranteed by design and is not tested.
When doing simulation, the clock signal in the waveform diagram is always low. I used the same method to program the clock signal in the previous simulation and there was no problem.
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FPGA/CPLD
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