iCE65
™
Ultra Low-Power
™
mobileFPGA Family
March 30, 2012 (2.42)
Data Sheet
First high-density, ultra low-power
Programmable Interconnect
Programmable Interconnect
I/O Bank 3
sources and methods
Processor-like mode self-configures from
external, commodity SPI serial Flash PROM
Downloaded by processor using SPI-like serial
interface in as little as 20 µs
In-system programmable, ASIC-like mode loads
from secure, internal Nonvolatile Configuration
Memory (NVCM)
Ideal for volume production
Superior design and intellectual property
protection; no exposed data
CMOS technology
Low leakage, µW static power
Lower core voltage, lowest dynamic power
4Kbit RAM
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
NVCM
Programmable Interconnect
I/O Bank 2
Nonvolatile Configuration
Memory (NVCM)
SPI
Config
Carry logic
Four-input
Look-Up Table
(LUT4)
Proven, high-volume 65 nm, low-power
JTAG
I/O Bank 1
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
Up to 256 MHz internal performance
Reprogrammable from a variety of
Flip-flop with enable
and reset controls
Flexible programmable logic and programmable
interconnect fabric
Over 7,600 look-up tables (LUT4) and flip-flops
Low-power logic and interconnect
Plentiful, fast, on-chip 4Kbit RAM blocks
Low-cost, space-efficient packaging options
Known-good die (KGD) options available
Complete iCEcube
™
development system
Windows
®
and Linux
®
support
VHDL and Verilog logic synthesis
Place and route software
Design and IP core libraries
Low-cost iCEman65 development board
Flexible I/O pins to simplify system interfaces
Up to 222 programmable I/O pins
Four independently-powered I/O banks; support for 3.3V,
2.5V, 1.8V, and 1.5V voltage standards
LVCMOS, MDDR, LVDS, and SubLVDS I/O standards
Table 1:
iCE65 Ultra Low-Power Programmable Logic Family Summary
iCE65L01
iCE65L04
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
RAM4K RAM bits
Configuration bits (maximum)
Typical Current at 0 kHz, 1.0 V
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
1,280
16
64K
245 Kb
12 µA
95
0
3,520
20
80K
533 Kb
26 µA
176
20
iCE65L08
7,680
32
128K
1,057 Kb
54 µA
222
25
© 2007-2012 by Lattice Semiconductor Corporation. All rights reserved.
www.latticesemi.com
(2.42, 30-MAR-2012)
1
8 Logic Cells = Programmable Logic Block
4Kbit RAM
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
single-chip, SRAM mobileFPGA family
specifically designed for hand-held
applications and long battery life
12 µA in static mode
Two power/speed options
–L: Low Power
–T: High speed
Figure 1:
iCE65 Family Architectural Features
12 µA at f =0
kHz
(Typical)
I/O Bank 0
Programmable Interconnect
Programmable
Logic Block (PLB)
iCE65 Ultra Low-Power mobileFPGA
™
Family
Overview
The Lattice Semiconductor iCE65 programmable logic family is specifically designed to deliver the lowest static and
dynamic power consumption of any comparable CPLD or FPGA device. iCE65 devices are designed for cost-
sensitive, high-volume applications and provide on-chip, nonvolatile configuration memory (NVCM) to customize
for a specific application. iCE65 devices can self-configure from a configuration image stored in an external
commodity SPI serial Flash PROM or be downloaded from an external processor over an SPI-like serial port.
The three iCE65 components, highlighted in
Table 1,
deliver from approximately 1K to nearly 8K logic cells and flip-
flops while consuming a fraction of the power of comparable programmable logic devices. Each iCE65 device
includes between 16 to 32 RAM blocks, each with 4Kbits of storage, for on-chip data storage and data buffering.
As pictured in
Figure 1,
each iCE65 device consists of four primary architectural elements.
An array of Programmable Logic Blocks (PLBs)
Each PLB contains eight Logic Cells (LCs); each Logic Cell consists of …
A fast, four-input look-up table (LUT4) capable of implementing any combinational logic function of
up to four inputs, regardless of complexity
A ‘D’-type flip-flop with an optional clock-enable and set/reset control
Fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and
counters.
Common clock input with polarity control, clock-enable input, and optional set/reset control input to
the PLB is shared among all eight Logic Cells
Two-port, 4Kbit RAM blocks (RAM4K)
256x16 default configuration; selectable data width using programmable logic resources
Simultaneous read and write access; ideal for FIFO memory and data buffering applications
RAM contents pre-loadable during configuration
Four I/O banks with independent supply voltage, each with multiple Programmable Input/Output (PIO)
blocks
LVCMOS I/O standards and LVDS outputs supported in all banks
I/O Bank 3 supports additional SSTL, MDDR, LVDS, and SubLVDS I/O standards
Programmable interconnections between the blocks
Flexible connections between all programmable logic functions
Eight dedicated low-skew, high-fanout clock distribution networks
(2.42, 30-MAR-2012)
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Lattice Semiconductor Corporation
www.latticesemi.com
Packaging Options
iCE65 components are available in a variety of package options to support specific application requirements. The
available options, including the number of available user-programmable I/O pins (PIOs), are listed in Table 2. Fully-
tested Known-Good Die (KGD) DiePlus
™
are available for die stacking and highly space-conscious applications. All
iCE65 devices are provided exclusively in Pb-free, RoHS-compliant packages.
Table 2:
iCE65 Family Packaging Options, Maximum I/O per Package
Package
Ball/Lead
Body
Package
Pitch
Package
65L01
(mm)
Code
(mm)
81-ball chip-scale BGA
5x5
CB81
0.5
63
(0)
84-pin quad flat no-lead package
7x7
QN84
0.5
67
(0)
100-pin very thin quad flat package
14 x 14
VQ100
0.5
72
(0)
121-ball chip-scale BGA
6x6
CB121
92
(0)
132-ball chip-scale BGA
8x8
CB132
93
(0)
0.5
196-ball chip-scale BGA
8x8
CB196
—
284-ball chip-scale BGA
12 x 12
CB284
—
See DiePlus
Known Good Die
DI
—
95
(0)
data sheet
= Common footprint allows each density migration on the same printed circuit board.
(Differential
65L04
—
—
72
(9)
—
95
(11)
150
(18)
176
(20)
176
(20)
65L08
—
—
—
—
95
(12)
150
(18)
222
(25)
222
(25)
input count)
.
The iCE65L04 and the iCE65L08 are both available in the CB196 package and have similar footprints but are not completely pin
compatible. See “Pinout
Differences between iCE65L04 and iCE65L08 in CB196 Package”
on page
73
for more information.
When iCE65 components are supplied in the same package style, devices of different gate densities share a common
footprint. The common footprint improves manufacturing flexibility. Different models of the same product can
share a common circuit board. Feature-rich versions of the end application mount a larger iCE65 device on the
circuit board. Low-end versions mount a smaller iCE65 device.
Lattice Semiconductor Corporation
www.latticesemi.com
(2.42, 30-MAR-2011)
3
iCE65 Ultra Low-Power mobileFPGA
™
Family
Ordering Information
Figure 2
describes the iCE65 ordering codes for all packaged, non-NVCM Programed components. See the separate
DiePlus data sheets when ordering die-based products.
Figure 2:
iCE65 Ordering Codes Standard Device
iCE65L 04 F -L CB 132 C
Logic Cells (x1,000)
04, 08
01, 04, 08
Configuration Memory
F
= NVCM + reprogrammable
Power Consumption/
Speed
-L
= Low power
-T
= High speed
Temperature Range
C
= Commercial
I
= Industrial
(T
A
= 0° to 70° Celsius)
J
(T
A
=
–40°
to 85° Celsius)
J
Package Leads
Package Style
CB
= chip-scale ball grid
CS
= wafer level chip-scale package (0.4 mm pitch)
VQ
= very-thin quad flat pack package
QN = quad flat no-lead package
iCE65 devices offer two power consumption, speed options. Standard products (“-L” ordering code) have low
standby and dynamic power consumption. The “-T” provides higher-speed logic.
Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications,
the other with an extended temperature range for industrial and telecommunications applications. The ordering
code also specifies the device package option, as described further in Table 2.
Figure 3
describes the iCE65 ordering codes for all packaged, NVCM Programmed components.
Figure 3:
iCE65 Ordering Codes NVCM Programmed Device
iCE65L 01 F – ZZZ ZZZZ
Logic Cells (x1000)
01, 04, 08
Configuration Memory
F = NVCM + reprogrammable
Customer Program Code
NVCM Program Code Revision
(2.42, 30-MAR-2012)
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Lattice Semiconductor Corporation
www.latticesemi.com
Programmable Logic Block (PLB)
Generally, a logic design for an iCE65 component is created using a high-level hardware description language such
as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description
into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential
and combinational functions are constructed from an array of Programmable Logic Blocks (PLBs). Each PLB
contains eight Logic Cells (LCs), as pictured in
Figure 4,
and share common control inputs, such as clocks, reset, and
enable controls.
PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources.
Logic Cell (LC)
Each iCE65 device contains thousands of Logic Cells (LCs), as listed in
Table 1.
Each Logic Cell includes three
primary logic elements, shown in
Figure 4.
A four-input
Look-Up Table (LUT4)
builds any combinational logic function, of any complexity, of up to
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and
cascade multiple LUT4s to create wider logic functions.
Figure 4:
Programmable Logic Block and Logic Cell
A
‘D’-style Flip-Flop (DFF),
with an optional clock-enable and reset control input, builds sequential logic
functions. Each DFF also connects to a global reset signal that is automatically asserted immediately
following device configuration.
Carry Logic
boosts the logic efficiency and performance of arithmetic functions, including adders,
subtracters, comparators, binary counters and some wide, cascaded logic functions.
The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block.
Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device.
Shared Block-Level Controls
Programmable Logic
Block (PLB)
Clock
Enable
Set/Reset
0
1
Logic Cell
DFF
D
Q
EN
SR
O
Carry Logic
I0
I1
I2
I3
8 Logic Cells (LCs)
LUT4
Four-input
Look-Up Table
(LUT4)
Flip-flop with
optional enable and
set or reset controls
= Statically defined by configuration program
Lattice Semiconductor Corporation
www.latticesemi.com
(2.42, 30-MAR-2011)
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