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74FCT162501CTPVG

Description
Bus Transceivers 18BIT REG TRANSCIVR
Categorylogic    logic   
File Size73KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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74FCT162501CTPVG Overview

Bus Transceivers 18BIT REG TRANSCIVR

74FCT162501CTPVG Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP, SSOP56,.4
Contacts56
Manufacturer packaging codePVG56
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresWITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
Control typeINDEPENDENT CONTROL
Counting directionBIDIRECTIONAL
seriesFCT
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length18.415 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits18
Number of functions1
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP56,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
method of packingTUBE
Peak Reflow Temperature (Celsius)260
power supply5 V
Prop。Delay @ Nom-Sup4.3 ns
propagation delay (tpd)4.4 ns
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
translateN/A
Trigger typePOSITIVE EDGE
width7.493 mm
IDT74FCT162501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
Balanced Output Drivers (±24mA)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
Available in SSOP and TSSOP packages
IDT74FCT162501AT/CT
DESCRIPTION:
The FCT162501T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and
OEBA),
latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is high. When LEAB is low, the A data
is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB
is the output enable for the B port. Data flow from the B port to the A port is similar
but requires using
OEBA,
LEBA and CLKBA. Flow-through organization of
signal pins simplifies layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT162501T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times–reducing the need for external series terminating resistors. The
FCT162501T is a plug-in replacement for the FCT16501T and ABT16501 for
on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
30
28
27
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
55
2
C
A
1
3
C
D
54
B
1
D
C
D
C
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2009 Integrated Device Technology, Inc.
SEPTEMBER 2009
DSC-2753/6

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Description Bus Transceivers 18BIT REG TRANSCIVR Bus Transceivers 18 BIT REG. TRANSCEIVER
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code SSOP TSSOP
package instruction SSOP, SSOP56,.4 TSSOP, TSSOP56,.3,20
Contacts 56 56
Manufacturer packaging code PVG56 PAG56
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Control type INDEPENDENT CONTROL INDEPENDENT CONTROL
Counting direction BIDIRECTIONAL BIDIRECTIONAL
series FCT FCT
JESD-30 code R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e3
length 18.415 mm 14 mm
Logic integrated circuit type REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
MaximumI(ol) 0.024 A 0.024 A
Humidity sensitivity level 1 1
Number of digits 18 18
Number of functions 1 1
Number of ports 2 2
Number of terminals 56 56
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output characteristics 3-STATE 3-STATE WITH SERIES RESISTOR
Output polarity TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP TSSOP
Encapsulate equivalent code SSOP56,.4 TSSOP56,.3,20
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing TUBE TAPE AND REEL
Peak Reflow Temperature (Celsius) 260 260
power supply 5 V 5 V
Prop。Delay @ Nom-Sup 4.3 ns 4.3 ns
propagation delay (tpd) 4.4 ns 4.4 ns
Certification status Not Qualified Not Qualified
Maximum seat height 2.794 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.635 mm 0.5 mm
Terminal location DUAL DUAL
Maximum time at peak reflow temperature 30 30
translate N/A N/A
Trigger type POSITIVE EDGE POSITIVE EDGE
width 7.493 mm 6.1 mm
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