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5P49V5907B508NDGI8

Description
Clock Generators & Support Products VersaClock 5 Low Pwr 4 Independent 0.7ps
Categorysemiconductor    Analog mixed-signal IC   
File Size426KB,30 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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5P49V5907B508NDGI8 Overview

Clock Generators & Support Products VersaClock 5 Low Pwr 4 Independent 0.7ps

5P49V5907B508NDGI8 Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerIDT (Integrated Device Technology)
Product CategoryClock Generators & Support Products
RoHSDetails
PackagingReel
Factory Pack Quantity2500
Programmable Clock Generator
5P49V5907
DATASHEET
Description
The 5P49V5907 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I C
addresses to allow multiple devices to be used in a system.
2
Features
Generates up to four independent output frequencies with a
total of 7 differential outputs and one reference output
Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency of
each output pair can be individually programmed
– Four copies of Low Power HCSL(LP-HCSL) outputs.
Programmable frequency:
– See Output Features and Descriptions for details
One reference LVCMOS output clock
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Pin Assignment
OUT0_SEL_I2CB
Four fractional output dividers (FODs)
Independent Spread Spectrum capability from each
OUT1
OUT1B
NC
OEB
6,7
V
DDO
0
V
DDO
1
V
DDO
2
OUT2
OUT2B
V
DD
V
DD
V
DD_CORE
OUT3
OUT3B
NC
NC
NC
XOUT
XIN/REF
V
DDA
V
DDO
OUT7
OUT7B
OUT6
OUT6B
SD/OE
1
2
3
4
5
6
7
8
9
40 39 38 37 36 35 34 33 32 31
30
29
28
27
fractional output divider (FOD)
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
OE_buffer
V
DDO
V
DD
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
EPAD
26
25
24
23
22
21
17 18 19 20
10
11 12 13 14 15 16
SEL0/SCL
SEL1/SD
OUT5B
OUT4B
V
DDO
OEB
3,5
OUT5
V
DDO
4
OUT4
V
DD
Programmable loop bandwidth
Programmable crystal load capacitance
Power-down mode
Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 4 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
40-pin VFQFPN
Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)
-40° to +85°C industrial temperature operation
5P49V5907 MARCH 3, 2017
1
©2017 Integrated Device Technology, Inc.
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