At 25°C ambient temperature. Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions
beyond those listed in the Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted. Test conditions
are per the specifications within the individual product electrical characteristics.
Functional Block Diagram
V
IN
V
OUT
Simplified Block Diagram (I
2
C™ pins SCL, SDA, ADR0, and ADR1 only active for PI33xx-20 device versions)
Cool-Power
®
ZVS Switching Regulators
Page 4 of 41
Rev 2.5
06/2017
PI33xx-x0
Pin Description
Pin Name
SGND
PGND
VIN
VOUT
VS1
PWRGD
EAO
EN
REM
ADJ
TRK
NC
VDR
SYNCO
SYNCI
SDA
SCL
ADR1
ADR0
Number
Block 1
Block 2
Block 3
Block 5
Block 4
A1
A2
A3
A5
B1
C1
A4
K3
K4
K5
D1
E1
H1
G1
Description
Signal Ground:
Internal logic ground for EA, TRK, SYNCI, SYNCO, ADJ and I
2
C (options) communication returns. SGND
and PGND are star connected within the regulator package.
Power Ground:
V
IN
and V
OUT
power returns.
Input Voltage:
and sense for UVLO, OVLO and feed forward ramp.
Output Voltage:
and sense for power switches and feed-forward ramp.
Switching Node:
and ZVS sense for power switches.
Power Good:
High impedance when regulator is operating and V
OUT
is in regulation.
Otherwise pulls to SGND. Also can be used for parallel timing management intended for lead regulator.
Error Amp Output:
External connection for additional compensation and current sharing.
Enable Input:
Regulator enable control. Asserted high or left floating – regulator enabled;
Asserted low, regulator output disabled. Polarity is programmable via I
2
C interface.
Remote Sense:
High side connection. Connect to output regulation point.
Adjust Input:
An external resistor may be connected between ADJ pin and SGND or VOUT
to trim the output voltage up or down.
Soft-start and Track Input:
An external capacitor may be connected between TRK pin
and SGND to decrease the rate of rise during soft-start.
No Connect:
Leave pins floating.
VDR can only be used for ADR0 and ADR1 pull up reference voltage.
No other external loading is permitted
Synchronization Output:
Outputs a low signal for ½ of the minimum period for synchronization of other converters.
Synchronization Input:
Synchronize to the falling edge of external clock frequency.
SYNCI is a high impedance digital input node and should always be connected to SGND when not in use.
Data Line:
Connect to SGND for PI33xx-00. For use with PI33xx-20 only.
Clock Line:
Connect to SGND for PI33xx-00. For use with PI33xx-20 only.
Tri-state Address:
No connect for PI33xx-00. For use with PI33xx-20 only.
Tri-state Address:
No connect for PI33xx-00. For use with PI33xx-20 only.
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