S3C9688/P9688
PRODUCT OVERVIEW
1
devices.
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated
peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for
applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time
operations. Many SAM88RCRI microcontrollers have an external interface that provides access to external memory and other peripheral
S3C9688/P9688 MICROCONTROLLER
The S3C9688/P9688 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful
SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal
register file was logically expanded. The S3C9688 has 8 K bytes of program
memory on-chip.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
—
—
—
—
Five configurable I/O ports (32 pins)
20 bit-programmable pins for external interrupts
8-bit timer/counter with three operating modes
Low speed USB function
The S3C9688/P9688 is a versatile microcontroller that can be used in a wide range of low speed USB support general purpose applications. It
is especially suitable for use as a keyboard controller and is available in a 42-pin SDIP and a 44-pin QFP package.
OTP
The S3C9688/P9688 microcontroller is also available in OTP (One Time Programmable) version, S3P9688. S3P9688 microcontroller has an
on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P9688 is comparable to S3C9688/P9688, both in function
and in pin configuration.
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PRODUCT OVERVIEW
S3C9688/P9688
FEATURES
CPU
•
SAM88RCRI CPU core
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval generation
function
•
Memory
•
One 8-bit timer/counter with Compare/Overflow
•
•
8 K byte internal program memory (ROM)
USB Serial Bus
208 byte RAM
•
•
•
Compatible to USB low speed (1.5 Mbps) device 2.0
specification.
Instruction Set
•
•
1 Control endpoint and 2 Interrupt endpoint
Serial bus interface engine (SIE)
—
Packet decoding/generation
CRC generation and checking
NRZI encoding/decoding and bit-stuffing
41 instructions
IDLE and STOP instructions added for power-down modes
Instruction Execution Time
—
—
•
0.66
µ
s at 6 MHz f
OSC
•
Interrupts
8 bytes each receive/transmit USB buffer
•
•
29 interrupt sources with one vector, each source has its
pending bit
One level, one vector interrupt structure
Low Voltage Reset
•
•
Low voltage detect for RESET
Power on Reset
Oscillation Circuit
Operating Temperature Range
•
•
•
6 MHz crystal/ceramic oscillator
External clock source (6 MHz)
•
– 40
°
C to + 85
°
C
Operating Voltage Range
Embedded oscillation capacitor (XI, XO, 33pF)
•
4.0 V to 5.25 V
General I/O
•
Package Types
Bit programmable five I/O ports (34 pins total)
—
(D+/PS2, D-/PS2 Included)
•
•
42-pin SDIP
44-pin QFP
Timer/Counter
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S3C9688/P9688
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7/INT2
P1.0-P1.7
P2.0-P2.7/INT0
Port 0
Port 1
Port 2
SAM88RCRI Bus
X
IN
Main
OSC
X
OUT
I/O Port and Interrupt Control
Port 3
P3.0
P3.1
P3.2
P3.3/CLO
Basic
Timer
Port 4
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
SAM88RCRI CPU
LVR
D+/PS2
USB
Timer
208-Byte
Register File
D-/PS2
3.3 V OUT
4 K/8KB ROM
40 bytes
USB
Buffer
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9688/P9688
PIN ASSIGNMENTS
P3.1
P3.0
INT0/P2.0
INT0/P2.1
INT0/P2.2
INT0/P2.3
INT0/P2.4
INT0/P2.5
INT0/P2.6
INT0/P2.7
V
DD
V
SS
X
OUT
X
IN
TEST
INT1/P4.0
INT1/P4.1
RESET
INT1/P4.2
INT1/P4.3
P1.7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
P3.2
P3.3/CLO
D+/PS2
D-/PS2
3.3V
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4/INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
OUT
S3C9688/P9688
(42-SDIP)
34
33
32
31
30
29
28
27
26
25
24
23
22
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
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S3C9688/P9688
PRODUCT OVERVIEW
3.3V
OUT
34
35
36
37
38
39
40
41
42
43
44
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4/INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P4.3/INT1
P4.2/INT1
RESET
D- /PS2
D+/PS2
CLO/P3.3
P3.2
P3.1
P3.0
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
S3C9688/P9688
44-QFP
(Top View)
18
17
16
15
14
13
12
NOTE:
The TEST pin must connect to V
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
INT0/P2.4
INT0/P2.5
INT0/P2.6
INT0/P2.7
V
DD
V
SS
X
OUT
X
IN
TEST
INT1/P4.0
INT1/P4.1
SS
1
2
3
4
5
6
7
8
9
10
11
(GND) in the normal operation mode.
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