IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
256K x 32, 256K x 36, 512K x 18
8Mb SYNCBURST Flow throughSRAMs
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
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Flowthrough Mode operation.
User-selectable Output Drive Strength with XQ Mode.
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and control
Pentium™ or linear burst sequence control using
MODE input
Common data inputs and data outputs
JEDEC 100-Pin TQFP and 119-pin PBGA package
Single +3.3V, +10%, –5% core power supply
Power-down snooze mode
2.5V or 3.3V I/O Supply
Snooze MODE for reduced-power standby
T version (three chip selects)
D version (two chip selects)
DESCRIPTION
ICSI's 8Mb SyncBurst Flowthrough SRAMs integrate a 512k x
18, 256k x 32, or 256k x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Applications
The ICSI SyncBurst Flowthrough SRAM family employs high-
speed ,low-power CMOS designs that are fabricated using an
advanced CMOS process to provide Level 2 Cache applica-
tions supporting Pentium and PowerPC microprocessors
originally, the device now finds application ranging from DSP
main store to networking chip set support.
Controls
All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.Bursts can be initiated
with either
ADSP
(Address Status Processor) or
ADSC
(Address
Status Cache Controller) input pins. Subsequent burst ad-
dresses can be generated internally and controlled by the
ADV
(burst address advance) input pin. The mode pin is used to select
the burst sequence order, Linear burst is achieved when this pin
is tied LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
Byte Write and Global Write
Write cycles are internally self-timed and are initiated by the rising
edge of the clock input. Write cycles can be from one to four bytes
wide as controlled by the write control inputs.Separate byte
enables allow individual bytes to be written. Byte write operation
is performed by using byte write enable (BWE).input combined
with one or more individualbyte write signals (BWx). In addition,
Global Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
IOL/IOH Drive strength Options
The XQ pin allows selection between high drive strength (XQ
low) for multi-drop bus applications and normal drive strength
(XQ floating or high) point-to-point applications. See the Output
Driver Characteristics chart for details.
Snooze Mode
Low power (Snooze mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK). Memory
data is retained during Snooze mode.
FAST ACCESS TIME
Symbol -6.5
6.5
Flow
t
KQ
Through t
KC
7.5
2-1-1-1 I
CC
1
270
-7.5
7.5
8.5
260
-8.5
8.5
10
240
-9.5
9.5
11
230
Units
ns
ns
mA
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
NC
NC
NC
NC
NC
VCCQ
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
NC
A10
SA
SA
SA
SA
SA
SA
100-Pin TQFP (D Version)
6
7
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
SA
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
2
3
4
5
SA
CE2
SA
NC
DQc3
DQc4
DQc6
DQc8
VCC
DQd2
DQd3
DQd5
DQd7
NC
SA
NC
SA
SA
SA
GND
GND
GND
BWc
GND
NC
GND
BWd
GND
GND
GND
MODE
SA
ADSP
ADSC
VCC
XQ
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
SA
SA
SA
SA
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
GND/NC
SA
SA
SA
SA
NC
DQb6
DQb5
DQb4
DQb2
VCC
DQa7
DQa5
DQa4
DQa3
NC
SA
NC
VCCQ
NC
NC
DQb8
DQb7
VCCQ
DQb3
DQb1
VCCQ
DQa8
DQa6
VCCQ
DQa2
DQa1
NC
ZZ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
Note:Ball R5 no connection is acceptable
256K x 32
Note:Pin 14 no connection is acceptable
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
XQ
V
CC
GND
V
CCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
A2-A17
CLK
ADSP
ADSC
ADV
BWa
-BWd
BWE
GW
CE
, CE2
OE
4
Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
SA
SA
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
SA
SA
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND/NC
VCC
XQ
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
SA
SA
SA
SA
A1
A0
NC
NC
GND
VCC
NC
SA
SA
SA
SA
SA
SA
SA
SA
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
Note:Pin 14 no connection is acceptable
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
DQa-DQd
MODE
XQ
V
CC
GND
V
CCQ
ZZ
Synchronous Data Input/Output
Burst Sequence Mode Selection
Output Drive Control
+3.3V Power Supply
Ground
Isolated Output Buffer Supply : +3.3V
or 2.5V
Snooze Enable
A2-A17
CLK
ADSP
ADSC
ADV
BWa
-BWd
BWE
GW
CE,CE2,CE2
OE
Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002
5
Embedded System
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