CMOS ST-BUS
TM
Family
MT90820
Large Digital Switch
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
2,048
×
2,048 channel non-blocking switching at
8.192 Mb/s
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI interfaces
Accept ST-BUS streams of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Control interface compatible to Motorola non-
mulitplexed CPUs
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
Ordering Information
MT90820AP
84 Pin PLCC
MT90820AL
100 Pin MQFP
MT90820APR
84 Pin PLCC
MT90820AL1
100 Pin MQFP*
MT90820AP1
84 Pin PLCC*
MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
Tubes
Trays
Tape & Reel
Trays
Tubes
Tape & Reel
August 2005
-40°C to +85°C
Applications
•
•
•
•
•
•
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
V
DD
V
SS
TMS
TDI
TDO
TCK
TRST
IC
RESET
ODE
Test Port
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
Serial
to
Parallel
Converter
Loopback
Parallel
Multiple Buffer
Data Memory
Output
MUX
to
Serial
Converter
Internal
Registers
Connection
Memory
Timing
Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS
HCLK
AS/ IM DS/ CS
ALE
RD
R/W
/WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT90820
Description
Data Sheet
The MT90820 Large Digital Switch has a non-blocking switch capacity of 2,048 x 2,048 channels at a serial bit rate
of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. The device has many
features that are programmable on per stream or per channel basis, including message mode, input offset delay
and high impedance output control.
Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice
channel and concatenated data channels.
In addition, input stream can be individually calibrated for input frame offset using a dedicated pin.
2
Zarlink Semiconductor Inc.
MT90820
Data Sheet
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
FE/HCLK
VSS
CLK
VDD
VSS
STo15
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
10
13
15
17
19
21
23
25
27
29
31
34
36
38
40
42
44
46
48
50
52
8
6
4
2
84
82
80
78
76
73
71
69
67
84 PIN PLCC
65
63
61
59
57
55
CSTo
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
NC
NC
NC
VSS
STo15
STo14
STo13
STo12
STo11
STo10
STo9
STo8
VDD
VSS
STo7
STo6
STo5
STo4
STo3
STo2
STo1
STo0
ODE
VSS
CSTo
NC
NC
NC
NC
80
82
48
84
46
86
44
88
42
90
92
94
36
96
34
98
99
2
4
6
8
10
12
14
16
18
20
22
24
26
28
32
30
78
76
74
72
70
68
66
64
62
60
58
56
54
52
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
R/W/RW
CS
AS/ALE
IM
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
F0i
FE/HCLK
VSS
CLK
50
100 PIN MQFP
40
38
DTA
D15
D14
D13
D12
D11
D10
D9
D8
VSS
VDD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSS
NC
NC
NC
NC
VDD
TMS
TDI
TDO
TCK
TRST
IC
RESET
WFPS
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
R/W/RW
CS
AS/ALE
IM
NC
NC
NC
NC
Figure 2 - Pin Connections
3
Zarlink Semiconductor Inc.
MT90820
Pin Description
Pin #
84
PLCC
1, 11,
30, 54
64, 75
2, 32,
63
3 - 10
100
MQFP
31, 41,
56, 66,
76, 99
5, 40,
67
68-75
Name
Description
Data Sheet
V
SS
Ground.
V
DD
STo8 - 15
+5 Volt Power Supply.
ST-BUS Output 8 to 15 (Three-state Outputs):
Serial data Output stream. These
streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value
programmed at bits DR0 - 1 in the IMS register.
ST-BUS Input 0 to 15 (Inputs):
Serial data input stream. These streams may have data
rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 -
1 in the IMS register.
Frame Pulse (Input):
When the WFPS pin is low, this input accepts and automatically
identifies frame synchronization signals formatted according to ST-BUS and GCI
specifications. When the WFPS pin is high, this pin accepts a negative frame pulse which
conforms to WFPS formats.
Frame Evaluation / HCLK Clock (Input):
When the WFPS pin is low, this pin is the
frame measurement input. When the WFPS pin is high, the HCLK (4.096 MHz clock) is
required for frame alignment in the wide frame pulse (WFP) mode.
Clock (Input):
Serial clock for shifting data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input
accepts a 4.096, 8.192 or 16.384 MHz clock.
Test Mode Select (Input):
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up when not driven.
Test Serial Data In (Input):
JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up when not driven.
Test Serial Data Out (Output):
JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enable.
Test Clock (Input):
Provides the clock to the JTAG test logic. This pin is pulled high by
an internal pull-up when not driven.
Test Reset (Input):
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This
pin should be pulsed low on power-up, or held low, to ensure that the MT90820 is in the
normal functional mode.
Internal Connection (Input):
Connect to V
SS
for normal operation. This pin must be
low for the MT90820 to function normally and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
12 - 27
81-96
STi0 - 15
28
97
F0i
29
98
FE/HCLK
31
100
CLK
33
34
35
36
37
6
7
8
9
10
TMS
TDI
TDO
TCK
TRST
38
11
IC
4
Zarlink Semiconductor Inc.
MT90820
Pin Description
Pin #
84
PLCC
39
100
MQFP
12
Name
Description
Data Sheet
RESET
Device Reset (Schmitt Trigger Input):
This input (active LOW) puts the MT90820 in
its reset state that clears the device internal counters, registers and brings STo0 - 15 and
microport data outputs to a high impedance state. The time constant for a power up reset
circuit must be a minimum of five times the rise time of the power supply. In normal
operation, the RESET pin must be held low for a minimum of 100 nsec to reset the
device.
Wide Frame Pulse Select (Input):
When 1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in ST-BUS/GCI mode.
Address 0 - 7 (Input):
When non-multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal memories.
Data Strobe / Read (Input):
For multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable the read and write operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input
works in conjunction with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This active low input sets the data bus
lines (AD0-AD7, D8-D15) as outputs.
Read/Write / Write (Input):
In the cases of Motorola non-multiplexed and multiplexed
bus operations, this input is R/W. This input controls the direction of the data bus lines
(AD0 - AD7, D8-D15) during a microprocessor access.
For multiplexed bus operation, this input is WR. This active low input is used with RD to
control the data bus (AD0 - 7) lines as inputs.
Chip Select (Input):
Active low input used by a microprocessor to activate the
microprocessor port of MT90820.
Address Strobe or Latch Enable (Input):
This input is used if multiplexed bus
operation is selected via the IM input pin. For Motorola non-multiplexed bus operation,
connect this pin to ground. This pin is pulled low by an internal pull-down when not
driven.
CPU Interface Mode (input):
When IM is high, the microprocessor port is in the
multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode.
This pin is pulled low by an internal pull-down when not driven.
Address/Data Bus 0 to 7 (Bidirectional):
These pins are the eight least significant data
bits of the microprocessor port. In multiplexed mode, these pins are also the input address
bits of the microprocessor port.
Data Bus 8-15 (Bidirectional):
These pins are the eight most significant data bits of the
microprocessor port.
Data Transfer Acknowledgement (Active Low Output):
Indicates that a data bus
transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is tri-stated.
Control Output (Output).
This is a 4.096, 8.192 or 16.384 Mb/s output containing 512,
1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo
bit in the connection memory. See External Drive Control Section.
40
41 - 48
49
13
14-21
22
WFPS
A0 - A7
DS/RD
50
23
R/W / WR
51
52
24
25
CS
AS/ALE
53
26
IM
55 - 62
32-39
AD0 - 7
65 - 72
73
42-49
50
D8 - 15
DTA
74
55
CSTo
5
Zarlink Semiconductor Inc.
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