IC43R16160
Document Title
4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
Revision History
Revision No
0A
0B
History
Initial Draft
Mass production
Draft Date
January 13,2004
November 10,2004
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004
1
IC43R16160
4M Words x 16 Bits x 4 Banks (256-MBIT)
DDR SYNCHRONOUS DYNAMIC RAM
5
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
DDR400
7.5ns
6ns
5ns
200MHz
6
DDR333
7.5ns
6ns
-
166MHz
7
DDR266
7.5ns
7ns
-
143MHz
Features
■
High speed data transfer rates with system frequency
up to 200 MHz
■
Data Mask for Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency: 2, 2.5, 3
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 66-pin 400 mil TSOP
■
SSTL-2 Compatible I/Os
■
Double Data Rate (DDR)
■
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
Differential clock inputs CK and CK
The ICSI IC43R16160 is a four bank DDR DRAM
organized as 4 banks x 4Mbit x 16. The IC43R16160
achieves high speed data transfer rates by employing a
chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, circuits are synchronized with
the positive edge of an externally supplied clock. I/O
transactions are ocurring on both edges of DQS. Operating
the four memory banks in an interleaved fashion allows
random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length,
CAS
latency and speed grade of the device.
Device Usage Chart
Operation
Temperature
Range
0°C to 70°C
Package Outline
JESEC 66TSOP II
•
CK Cycle Time (ns)
-5
•
-6
•
-7
•
Power
Std.
•
L
•
Temperature
Mark
Blank
2
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004
IC43R16160
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A 11
A9
A8
A7
A6
A5
A4
VSS
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
12
BA0, BA1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V
SS
V
DDQ
V
SSQ
NC
VREF
DQ’s
DM (UDM, LDM)
V
DD
Data Input/Output
Data Mask
Power
(+2.5V and +2.6V for DDR400)
Ground
Power for I/O’s
(+2.5V and +2.6V for DDR400)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004
3
IC43R16160
Block Diagram
16M x 16
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
8192 x 256
x32 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 256
x 32 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 256
x 32 bit
Column decoder
Sense amplifier & I(O) bus
8192 x 256
x 32 bit
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
15
RAS
CAS
WE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
Capacitance*
T
A
= 0 to 70°C, V
CC
= 2.5V
±
0.2V, V
CC
= 2.6V
±
0.1V
for DDR400, f = 1 Mhz
Input Capacitance
Symbol
Min
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 °C
Storage temperature range ................-55 to 150 °C
V
DD
Supply Voltage Relative to V
SS
.....-1V to +3.6V
V
DDQ
Supply Voltage Relative to V
SS
......................................................-1V to +3.6V
VREF and Inputs Voltage Relative to V
SS
......................................................-1V to +3.6V
I/O Pins Voltage Relative to V
SS
.......................................... -0.5V to V
DDQ
+0.5V
Power dissipation .......................................... 1.6 W
Data out current (short circuit) ...................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Max Unit
3.0
3.0
5
5.0
pF
pF
pF
pF
BA0, BA1, CKE, CS, RAS, (CAS,
A0-A11, WE)
Input Capacitance (CK, CK)
Data & DQS I/O Capacitance
Input Capacitance (DM)
C
INI
C
IN2
C
OUT
C
IN3
2
2
4
4
*Note: Capacitance is sampled and not 100% tested.
4
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004
CKE
DM
CK
CK
CS
IC43R16160
Signal Pin Description
Pin
CK
CK
CKE
Type Signal
Input
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising
edge of CK.
Activates the CK signal when high and deactivates the CK signal when low, thereby
initiates either the Power Down mode, or the Self Refresh mode.
CS
enables the command decoder when low and disables the command decoder
Input
Pulse Active Low when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
Pulse Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define
the command to be executed by the SDRAM.
Input
Level Active High
CS
RAS
,
CAS
Input
WE
DQS
Active on both edges for data input and output.
Input/
Pulse Active High Center aligned to input data
Output
Edge aligned to output data
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-
RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-
CA8) when sampled at the rising clock edge.
In addition to the column address, A10(=AP) is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high,
all four banks will be precharged simultaneously regardless of state of BA0 and BA1.
Selects which bank is to be active.
A0 - A12
Input
Level
_
BA0,
BA1
DQx
DM,
LDM,
UDM
Input
Level
_
Input/
Level
Output
_
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Input
In Write mode, DM has a latency of zero and operates as a word mask by allowing
Pulse Active High input data to be written if it is low but blocks the write operation if is high for LDM
corresponds to data on DQ0-DQ7, UDM corresponds to data on DQ8-DQ15.
Power and ground for the input buffers and the core logic.
_
Level
_
_
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
SSTL Reference Voltage for Inputs
VDD,VSS Supply
VDDQ
Supply
VSSQ
VREF
Input
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004
5
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