IC41SV44052
IC41SV44054
Preliminary
4M x 4 (16-MBIT) DYNAMIC RAM
WITH FAST PAGE MODE
FEATURES
• Fast Page Mode Access Cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
• Refresh Mode:
RAS-Only,
CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
1.9V
−
2.7V
DESCRIPTION
The
ICSI
44052/44054 Series is a 4,194,304 x 4-bit high-
performance CMOS Dynamic Random Access Memory. The
Fast Page Mode allows 2,048 or 4,096 random accesses within
a single row with access cycle time as short as 20 ns per 4-bit
word.
These features make the 44052/44054 Series ideally suited for
digital signal processing, and low power portable audio
applications.
The 44052/44054 Series is packaged in a 26-pin 300mil SOJ
and a 26 pin TSOP-2
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
Fast Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-70
-100
Unit
70
20
35
45
100
25
50
60
ns
ns
ns
ns
ns
130 180
PIN CONFIGURATION
24 (26) Pin SOJ, TSOP-2
VCC
I/O0
I/O1
WE
RAS
*A11(NC)
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
A0-A10
I/O0-3
WE
OE
RAS
CAS
Vcc
GND
Address Inputs (4K Refresh)
Address Inputs (2K Refresh)
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
*A11 is NC for 2K Refresh devices.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
IC41SV44052
IC41SV44054
Functional Description
The IC41SV44052 and IC41LV44054 are CMOS DRAMs
optimized for high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 or 12 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
or 12 bits (A0-A11) at a time for the 4K refresh device. The
row address is latched by the Row Address Strobe (RAS).
The column address is latched by the Column Address
Strobe (CAS).
RAS
is used to latch the first nine bits and
CAS
is used the latter ten bits.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 11(12)-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle
must not be initiated until the minimum precharge time t
RP
,
t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initializa-
tion cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The col-
umn address must be held for a minimum time specified by
t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and
t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs
last.
4
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
IC41SV44052
IC41SV44054
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Storage Temperature
Rating
−0.5
to +3.0
−0.5
to +3.0
50
0.2
-10 to +70
−55
to +125
Unit
V
V
mA
W
o
C
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Min.
1.9
1.6
−0.3
-10
Max.
2.7
V
CC
+ 0.3
0.6
70
Unit
V
V
V
o
C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A10
Input Capacitance:
RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz.
Integrated Circuit Solution Inc.
DR035-0B 7/31/2002
5
Talking
京公网安备 11010802033920号
EEWORLD
