November 2006
HYS64T16000HU–[3.7/5]–A
HYS72T32000HU–[2.5/25F/3/3S/3.7/5]–A
HYS64T32001HU–[2.5/25F/3/3S/3.7/5]–A
HYS[64/72]T64020HU–[2.5/25F/3/3S/3.7]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
UDIMM SDRAM
RoHs Compliant
Internet Data Sheet
Rev. 1.41
Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
HYS64T16000HU–[3.7/5]–A, HYS72T32000HU–[2.5/25F/3/3S/3.7/5]–A, HYS64T32001HU–[2.5/25F/3/3S/3.7/5]–A,
HYS[64/72]T64020HU–[2.5/25F/3/3S/3.7]–A
Revision History: 2006-11, Rev. 1.41
Page
All
All
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Product portfolio extended : Added -2.5F and -3.7 products
Chapter 1.1
Added features for average self refresh and self refresh rate to Feature list
Chapter 3
Chapter 3
Chapter 4
Chapter 4
Chapter 5
Updated
I
DD
Currents
Corrected note 4 - Table 18
Updated SPD Codes
SPD Codes update: Byte 49 Bit 0 = 1 (HighT_SRFEntry) for all product types
Package Outlines updated
Previous Revision: 2006-04, Rev. 1.4
Previous Revision: 2005-09, Rev. 1.3
Previous Revision: 2005-05, Rev. 1.2
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03062006-0GN5-WTPW
2
Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
• Programmable CAS Latencies (3, 4, 5 and 6), Burst
Length (4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
• Average Refresh Period 7.8 µs at a
T
CASE
lower than
85 °C, 3.9 µs between 85 °C and 95 °C
• Programmable self refresh rate via EMRS2 setting
• All inputs and outputs SSTL_18 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E
2
PROM
• UDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
• Based on standard reference layouts Raw Card “A”, “C”,
“D“, “E“, “F” and “G”
• RoHS compliant products
1)
• 240-Pin PC2–6400, PC2–5300, PC2–4200 and PC2–
3200 DDR2 SDRAM memory modules for use as main
memory when installed in systems such as mobile
personal computers.
• 16M
×
64, 32M
×
64, 32M
×
72, 64M
×
64, 64M
×
72
module organization and 16M
×
16, 32M
×
8 chip
organization
• 128 MB, 256 MB and 512 MB modules built with 256-Mbit
DDR2 SDRAMs in PG-TFBGA-60 and PG-TFBGA-84
chipsize packages
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• All Speed Grades faster than DDR2–400 comply with
DDR2–400 timing specifications
TABLE 1
Performance Table
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL6
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
–2.5
–3
–3S
–3.7
–5
Unit
PC2–6400 PC2–6400 PC2–5300 PC2–5300 PC2–4200 PC2–3200 —
5–5–5
6–6–6
4–4–4
5–5–5
4–4–4
3–3–3
f
CK6
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
400
400
266
200
12.5
12.5
45
57.5
400
333
266
200
15
15
45
60
–
333
333
200
12
12
45
57
–
333
266
200
15
15
45
60
–
266
266
200
15
15
45
60
–
200
200
200
15
15
40
55
MHz
MHz
MHz
MHz
ns
ns
ns
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
3
Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
1.2
Description
The memory array is designed with 256-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The QIMONDA HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
module family are unbuffered DIMM modules “UDIMMs” with
30,0 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 16M
×
64 (128MB),
32M
×
64 (256MB), 64M
×
64 (512MB) and as ECC modules
in 32M
×
72 (256MB), 64M
×
72 (512MB) organization and
density, intended for mounting into 240-pin connector
sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–6400
HYS64T32001HU–2.5–A
HYS64T64020HU–2.5–A
HYS72T32000HU–2.5–A
HYS72T64020HU–2.5–A
HYS64T32001HU–25F–A
HYS64T64020HU–25F–A
HYS72T32000HU–25F–A
HYS72T64020HU–25F–A
PC2–5300
HYS64T32001HU–3–A
HYS64T64020HU–3–A
HYS72T32000HU–3–A
HYS72T64020HU–3–A
HYS64T32001HU–3S–A
HYS64T64020HU–3S–A
HYS72T32000HU–3S–A
HYS72T64020HU–3S–A
PC2–4200
HYS64T16000HU–3.7–A
HYS64T32001HU–3.7–A
HYS72T32000HU–3.7–A
HYS64T64020HU–3.7–A
128MB 1Rx16 PC2–4200U–444–11–C1
256MB 1Rx8 PC2–4200U–444–11–A1
256MB 1Rx8 PC2–4200E–444–11–A1
512MB 2Rx8 PC2–4200U–444–12–E1
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
2 Ranks, Non-ECC
256 Mbit (x16)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256MB 1Rx8 PC2–5300U–444–12–D0
512MB 2Rx8 PC2–5300U–444–12–E0
256MB 1Rx8 PC2–5300E–444–12–F0
512MB 2Rx8 PC2–5300E–444–12–G0
256MB 1Rx8 PC2–5300U–555–12–D0
512MB 2Rx8 PC2–5300U–555–12–E0
256MB 1Rx8 PC2–5300E–555–12–F0
512MB 2Rx8 PC2–5300E–555–12–G0
1 Rank, Non-ECC
2 Ranks, Non-ECC
1 Rank, ECC
2 Ranks, ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
1 Rank, ECC
2 Ranks,ECC
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256MB 1Rx8 PC2–6400U–666–12–D0
512MB 2Rx8 PC2–6400U–666–12–E0
256MB 1Rx8 PC2–6400E–666–12–F0
512MB 2Rx8 PC2–6400E–666–12–G0
256MB 1Rx8 PC2–6400U–555–12–D0
512MB 2Rx8 PC2–6400U–555–12–E0
256MB 1Rx8 PC2–6400E–555–12–F0
512MB 2Rx8 PC2–6400E–555–12–G0
1 Rank, Non-ECC
2 Ranks, Non-ECC
1 Rank, ECC
2 Ranks, ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC
1 Rank, ECC
2 Ranks, ECC
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
256 Mbit (x8)
Compliance Code
2)
Description
SDRAM Technology
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
4
Internet Data Sheet
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
Product Type
1)
PC2–3200
HYS64T16000HU–5–A
HYS64T32001HU–5–A
HYS72T32000HU–5–A
Compliance Code
2)
128MB 1Rx16 PC2–3200U–333–11–C1
256MB 1Rx8 PC2–3200U–333–11–A1
256MB 1Rx8 PC2–3200E–333–11–A1
Description
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, ECC
SDRAM Technology
256 Mbit (x16)
256 Mbit (x8)
256 Mbit (x8)
1) All product types end with a place code, designating the silicon die revision. Example: HYS64T16000HU–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see
Chapter 6
of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–11–C1”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and
produced on the Raw Card “C”.
TABLE 3
Address Format
DIMM
Density
128 MByte
256 MByte
512 MByte
Module
Organization
16M
×
64
32M
×
64
32M
×
72
64M
×
64
64M
×
72
Memory
Ranks
1
1
1
2
2
ECC/
Non-ECC
Non-ECC
Non-ECC
ECC
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
4
8
9
16
18
13/2/9
13/2/10
13/2/10
13/2/10
13/2/10
Raw
Card
C
A,D
A,F
E
G
TABLE 4
Components on Modules
Product Type
1)
HYS64T16000HU
HYS64T32001HU
HYS64T64020HU
HYS72T32000HU
HYS72T64020HU
DRAM Components
1)
HYB18T256160AF
HYB18T256800AF
HYB18T256800AF
HYB18T256800AF
HYB18T256800AF
DRAM Density
256 Mbit
256 Mbit
256 Mbit
256 Mbit
256 Mbit
DRAM Organisation
16M
×
16
32M
×
8
32M
×
8
32M
×
8
32M
×
8
Note
2)
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
5
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