March 2007
HYS72T512022EP–3.7–B
HYS72T512022EP–3S–B
240-Pin Dual Die Registered DDR2 SDRAM Modules
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
HYS72T512022EP–3.7–B, HYS72T512022EP–3S–B
Revision History: 2007-03, Rev. 1.0
Page
All
All
Subjects (major changes since last revision)
Adapted internet edition
Final Document
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03292007-RHOW-C5L6
2
Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Dual Die Registered DDR2 SDRAM Modules with parity bit product family
and describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E
2
PROM
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
Based on standard reference card layouts Raw Card “K”
All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
RoHS compliant products
1)
• 240-Pin PC2–5300 and PC2–4200 DDR2 SDRAM
memory modules.
• 512M
×72
module organization and 2
×
256M
×
4 chip
organization
• Registered DIMM Parity bit for address and control bus
• 4GB modules built with 1Gbit DDR2 SDRAMs in
P-TFBGA-71 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length
(4 & 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
3
Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
1.2
Description
loading to the system bus, but adds one cycle to the SDRAM
timing. Decoupling capacitors are mounted on the PCB
board. The DIMMs feature serial presence detect based on a
serial E
2
PROM device using the 2-pin I
2
C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
The Qimonda HYS72T512022EP–[3S/3.7]–B module family
are Registered DIMM (with parity) modules with 30 mm height
based on DDR2 technology.
DIMMs are available as ECC modules in 512M
×
72 (4 GB)
organization and density, intended for mounting into 240-Pin
connector sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. All control and address
signals are re-driven on the DIMM using register devices and
a PLL for the clock distribution. This reduces capacitive
TABLE 1
Ordering Information for RoHS Compliant Products
Product Type
1)
PC2–4200
HYS72T512022EP–3.7–B
PC2–5300
HYS72T512022EP–3S–B
4 GB 2R×4 PC2–5300P–555–12–K0
2 Ranks, ECC
2
×
256 Mbit (×4)
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T512022EP–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see
Chapter 6
of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
Compliance Code
2)
Description
SDRAM
Technology
2
×
256 Mbit (×4)
4 GB 2R×4 PC2–4200P–444–12–K0
2 Ranks, ECC
TABLE 2
Address Format Table
DIMM
Density
4 GByte
Module
Organization
512M
×
72
Memory
Ranks
2
ECC/
Non-ECC
ECC
# of SDRAMs # of row/bank/column
bits
36
14/3/11
Raw
Card
K
TABLE 3
Components on Modules
Product Type
1)
HYS72T512022ER
DRAM Components
1)2)
HYB18T2G402BF
DRAM Density
2 × 1 Gbit
DRAM Organisation
2
×
256M
×
4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
4
Internet Data Sheet
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
2
Pin Configuration
and
Table 6
respectively. The pin numbering is depicted in
Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in
Table 4
(240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in
Table 5
TABLE 4
Pin Configuration of RDIMM
Ball No.
Clock Signals
185
186
52
171
CK0
CK0
CKE0
CKE1
NC
Control Signals
193
76
S0
S1
NC
192
74
73
18
Address Signals
71
190
54
BA0
BA1
BA2
NC
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
Not Connected
Less than 1Gb DDR2 SDRAMS
Bank Address Bus 1:0
RAS
CAS
WE
RESET
I
I
NC
I
I
I
I
SSTL
SSTL
—
SSTL
SSTL
SSTL
CMOS
Register Reset
Chip Select Rank 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
—
Clock Enables 1:0
Note: 2-Ranks module
Not Connected
Note: 1-Rank module
Clock Signal CK0, Complementary Clock Signal CK0
Name
Pin
Type
Buffer
Type
Function
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
5
MCU
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