HY5DU56822AT-M datasheet, PDF - EEWORLD Datasheet

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HY5DU56822AT-M: Description256M-S DDR SDRAM; Categorystorage storage; File Size364KB，36 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY5DU56822AT-M Overview

256M-S DDR SDRAM

HY5DU56822AT-M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSSOP66,.46
Contacts	66
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
JESD-609 code	e6
length	22.225 mm
memory density	268435456 bi
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	66
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.02 A
Maximum slew rate	0.315 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Bismuth (Sn/Bi)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	10.16 mm

HY5DU56822AT-M Preview

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

256M-S DDR SDRAM

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume

any responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.4/ May. 02

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

Revision History

1. Revision 0.2 (Jan. 02)

1) Define Preliminary Specification

2. Revision 0.3 (Mar. 02)

1) Define IDD Specification

2) Added programmable Cas Latrency 1.5

3) Changed V

REF

value from min (0.49*V

DDQ)

& max (0.51*V

DDQ)

to min (V

DDQ

/2-50mV) & max (V

DDQ

/2+50mV)

4) Changed I

(Input Leakage Current) value from +/- 5uA to +/- 2uA

3. Revision 0.4 (May. 02)

1) Added comment of Cas Latrency 1.5 & 3

Rev. 0.4/ May. 02

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

DESCRIPTION

PRELIMINARY

The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Syn-

chronous DRAM, ideally suited for the main memory applications which requires large memory density and high band-

width.

The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,

Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible

with SSTL_2.

FEATURES

•

, V

DDQ

= 2.5V +/- 0.2V

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous - data transaction aligned to

bidirectional data strobe (DQS)

x16 device has two bytewide data strobes (UDQS,

LDQS) per each x8 I/O

Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (centered

DQ)

On chip DLL align DQ and DQS transition with CK

transition

DM mask write data-in at the both rising and falling

edges of the data strobe

•

All addresses and control inputs except data, data

strobes and data masks latched on the rising edges

of the clock

Programmable CAS latency 1.5, 2, 2.5 and 3

supported

Programmable burst length 2 / 4 / 8 with both

sequential and interleave mode

Internal four bank operations with single pulsed

/RAS

tRAS Lock-out function supported

Auto refresh and Self refresh supported

8192 refresh cycles / 64ms

JEDEC standard 400mil 66pin TSOP-II with 0.65mm

pin pitch

Full and Half strength driver option controlled by

EMRS

•

ORDERING INFORMATION

Part No.

HY5DU56422A(L)T-X*

HY5DU56822A(L)T-X*

HY5DU561622A(L)T-X*

OPERATING FREQUENCY

Package

400mil

66pin

TSOP-II

Configuration

64Mx4

32Mx8

16Mx16

Grade

-J

-M

-K

-H

-L

CL2

133MHz

100MHz

CL2.5

166MHz

133MHz

125MHz

Remark

(CL-tRCD-tRP)

DDR333 (2.5-3-3)

DDR266 (2-2-2)

DDR266A (2-3-3)

DDR266B (2.5-3-3)

DDR200 (2-2-2)

* X means speed grade

* CL1.5 @ DDR200 supported

* CL3 supported

Rev. 0.4 / May. 02

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

PIN CONFIGURATION

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

VDD

DNU

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

VDD

DQ0

VDDQ

DQ1

VSSQ

DQ2

VDDQ

DQ3

VSSQ

VDDQ

VDD

DNU

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

VDD

x16

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDDQ

LDQS

VDD

DNU

LDM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

VDD

x16

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSSQ

UDQS

VREF

VSS

UDM

/CK

CKE

A12

A11

VSS

DQ7

VSSQ

DQ6

VDDQ

DQ5

VSSQ

DQ4

VDDQ

VSSQ

DQS

VREF

VSS

/CK

CKE

A12

A11

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSSQ

DQS

VREF

VSS

/CK

CKE

A12

A11

VSS

400mil X 875mil

66pin TSOP -II

0.65mm pin pitch

ROW AND COLUMN ADDRESS TABLE

ITEMS

Organization

Row Address

Column Address

Bank Address

Auto Precharge Flag

Refresh

64Mx4

16M x 4 x 4banks

A0 - A12

A0-A9, A11

BA0, BA1

A10

32Mx8

8M x 8 x 4banks

A0 - A12

A0-A9

BA0, BA1

A10

16Mx16

4M x 16 x 4banks

A0 - A12

A0-A8

BA0, BA1

A10

Rev. 0.4/ May. 02

HY5DU56422A(L)T

HY5DU56822A(L)T

HY5DU561622A(L)T

PIN DESCRIPTION

CK, /CK

TYPE

Input

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A10 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ

and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-

sponds to the data on DQ8-Q15.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. For the x16, LDQS corresponds to the

data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.

Data input / output pin : Data bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CKE

Input

/CS

Input

BA0, BA1

Input

A0 ~ A12

Input

/RAS, /CAS, /WE

Input

(LDM, UDM)

Input

DQS

(LDQS, UDQS)

DDQ

SSQ

REF

I/O

Supply

Rev. 0.4/ May. 02

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