The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V281620A is organized as 4banks of 2,097,152x16
HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
•
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
•
ORDERING INFORMATION
Part No.
HY57V281620AT-6
HY57V281620AT-7
HY57V281620AT-K
HY57V281620AT-H
HY57V281620AT-8
HY57V281620AT-P
HY57V281620AT-S
HY57V281620ALT-6
HY57V281620ALT-7
HY57V281620ALT-K
HY57V281620ALT-H
HY57V281620ALT-8
HY57V281620ALT-P
HY57V281620ALT-S
Clock Frequency
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
143MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits de-
scribed. No patent licenses are implied.
Rev. 1.3/Aug. 01
HY57V281620A
PIN CONFIGURATION
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN
CLK
Clock
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
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