Data Sheet: ACD82124
24 Ports 10/100 Fast Ethernet Switch Controller
Rev.1.1.1.F
Last Update: November 5, 1998
Subject to Change
Please check ACD’s website for
update information before starting a design
Web site: http://www.acdcorp.com
or Contact ACD at:
Email: support@acdcorp.com
Tel: 408-433-9898x115
Fax: 408-545-0930
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
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ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
INTRODUCTORY
Data Sheet: ACD82124
Advanced
Communication
Devices
Table of Contents
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3
4
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7
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9
10
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General Description
Main Features
System Block Diagram
System Description
Functional Description
Interface Description
Register Description
Pin Description
Timing Description
Electrical Specifications
Packaging
Appendix
Address Resolution Logic
(The built-in ARL)
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16
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38
39
A1
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ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
2
INTRODUCTORY
Section
Page
Data Sheet: ACD82124
1. GENERAL DESCRIPTION
The ACD82124 is a single chip implementation of a 24
port 10/100 Ethernet switch system intended for IEEE
802.3 and 802.3u compatible networks. The device
includes 24 independent 10/100 MACs. Each MAC
interfaces with an external PMD/PHY device through a
standard MII interface. Speed can be automatically
configured through the MDIO port. Each port can op-
erate at either 10Mbps or 100Mbps. The core logic of
the ACD82124, implemented with patent pending
BASIQ (Bandwidth Assured Switching with Intelligent
Queuing) technology, can simultaneously process 24
asynchronous 10/100Mbps port traffic. The Queue
Manager inside the ACD82124 provides the capability
of routing traffic with the same order of sequence,
without any packet loss.
A complete 24 port 10/100 switch can be built with the
use of the ACD82124, 10/100 PHY and ASRAM. The
MAC addresses can be expanded from the built-in 2K
to 11K by the use of ACD’s external ARL chip
(ACD80800 Address Resolution Logic). Advanced net-
work management features can be supported with the
use of ACD’s MIB (ACD80900 Management Informa-
tion Base) chip.
2. FEATURES
Data Sheet: ACD82124
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
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3. SYSTEM BLOCK DIAGRAM
FIFO
MAC-0
FIFO
Buffer
Buffer
Lookup Engine
(2K MAC Addr.)
BIST Handler
LED Controller
PMD/
PHY-0
PMD/
PHY-1
FIFO
MAC-1
FIFO
Buffer
Buffer
MX
Queue Manager
DMX
FIFO
MAC-22
FIFO
Buffer
Buffer
PMD/
PHY-22
PMD/
PHY-23
FIFO
MAC-23
FIFO
Buffer
Buffer
ARL Interface
SRAM Interface
MIB Interface
ACD82124
ARL
ACD80800
(11K MAC Addr.)
(optional)
SRAM
MIB
ACD80900
(optional)
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INTRODUCTORY
24 ports 10/100 auto-sensing with MII interface
Half-duplex operation, with optional full-duplex con-
figuration by combining 2 adjacent ports
2.4 Gbps aggregated throughput
True non-blocking switch architecture
Flexible port configuration (up to 12 full duplex 10/
100 ports, up to 24 half duplex 10/100 ports)
Built-in storage of 2,000 MAC address
Automatic source address learning
Zero-Packet Loss back-pressure flow control
Store-and-forward switch mode
Port based V-LAN support
UART type CPU management interface
Supports up to 11K MAC addresses with the
ACD80800
RMON and SNMP support with ACD80900
Status LEDs: Link, Speed, Full Duplex, Transmit,
Receive, Collision and Frame Error
Reversible MII option for CPU and expansion port
interface
Wire speed forwarding rate
576 pin BGA package
3.3V power supply, 3.3V I/O with 5V tolerance
4. SYSTEM DESCRIPTION
The ACD82124 is a single chip implementation of a
24-port Fast Ethernet switch. Together with external
ASRAM and transceiver devices, it can be used to
build a complete desktop class Fast Ethernet switch.
Each individual port can be either auto-sensed or manu-
ally selected to run at 10 Mbps or 100 Mbps speed
rate, under Half Duplex mode.
The ACD82124 Ethernet switch contains three major
functional blocks: the Media Access Controller (MAC),
the Queue Manager, and the Lookup Engine.
There are 24 independent MACs within the ACD82124.
The MAC controls the receiving, transmitting, and de-
ferring process of each individual port, in accordance
to IEEE 802.3 and 802.3u standard. The MAC logic
also provides framing, FCS checking, error handling,
status indication and back-pressure flow control func-
tions. Each MAC interfaces with an external transceiver
through standard MII interface.
The device utilizes ACD’s proprietary BASIQ (Band-
width Assured Switching with Intelligent Queuing) tech-
nology. It is a technology to enforce the first-in-first-
out rule of Ethernet Bridge-type devices in a very effi-
cient way. The technology enables a true non-block-
ing frame switching operation at wire speed for a high
throughput and high port density Ethernet switch.
The on-chip 2,000 MAC addresses Lookup Engine
maps each destination address into a destination port.
Each port’s MAC address is automatically learned by
the Lookup Engine when it receives a frame with no
error. Therefore, the ACD82124 alone can be used to
build a desktop class Fast Ethernet switch without any
additional switching devices.
Among the 24 MII interfaces, 10 of them can be con-
figured as reversed MII, to connect directly with stand-
alone MAC controller devices. A MAC in the ACD82124
can be viewed logically as a PHY device if it is config-
ured as a reversed MII interface. The reversed MII is
intended for a CPU network interface, or expansion
port interface.
A system CPU can access various registers inside
the ACD82124 through a serial CPU management
interface. The CPU can configure the switch by
writing into the appropriate registers, or retrieve the
status of the switch by reading the corresponding
registers. The CPU can also access the registers of
external transceiver (PHY) devices through the CPU
management interface.
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ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
INTRODUCTORY
The ACD82124 provides management support through
its MIB (Management Information Base) interface. The
MIB interface can be used to monitor all traffic activi-
ties of the switch system. ACD’s supporting chip (the
ACD80900) provides a full set of statistical counters to
support both SNMP and RMON network management.
The MIB interface can also be used by system de-
signers to implement vendor-specific network manage-
ment functionality.
Data Sheet: ACD82124
The MAC address space can be expanded from 2,000
to 8,000 per system by using the ACD80800. The
ACD82124 has a proprietary ARL interface that allows
direct connection with ACD80800. System designers
can also use this ARL interface to implement a ven-
dor-specific address resolution algorithm.
5. FUNCTIONAL DESCRIPTION
The MAC controller performs transmit, receive, and
defer functions, in accordance to IEEE 802.3 and
802.3u standard specification. The MAC logic also
handles frame detection, frame generation, error de-
tection, error handling, status indication and flow con-
trol functions.
Frame Format
The ACD82124 assumes that the received data packet
will have the following format:
Start of Frame Detection
When a port’s MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the re-
ceive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock
(25Mhz or 2.5MHz). The ACD82124 will convert this
data into a serial bit stream, and attempt to detect the
occurrence of the SFD (10101011) pattern. All data
prior to the detection of SFD are discarded. Once SFD
is detected, the following frame data are forwarded
and stored in the buffer of the switch.
Data Sheet: ACD82124
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Frame Reception
Preamble SFD DA SA Type/Len Data FCS
Under normal operating conditions, the ACD82124
expects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
80 BT (Bit Time).
In the event the ACD82124 receives a packet with IFG
less than 80BT, the ACD82124 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82124 cannot receive the frame.
The device will check all received frames for errors
such as symbol error, FCS error, short event, runt,
long event, jabber etc. Frames with any kind of error
will not be forwarded to any port.
Where,
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Preamble
is a repetitive pattern of ‘1010….’ of
any length with nibble alignment.
SFD
(Start Frame Delimiter) is defined as an oc-
tet pattern of 10101011.
DA
(Destination Address) is a 48-bit field that speci-
fies the MAC address of the destined DTE. If the
first bit of DA is 1, the ACD82124 will treat the
frame as a broadcast/multicast frame and will for-
ward the frame to all ports within the source port’s
VLAN except the source port itself or BPDU ad-
dress.
SA
(Source Address) is a 48-bit field that con-
tains the MAC address of the source DTE that is
transmitting the frame to the ACD82124. After a
frame is received with no error, the SA is learned
as the port’s MAC address.
Type/Len
field is a 2-byte field that specifies the
type (DIX Ethernet frame) or length (IEEE 802.3
frame) of the frame. The ACD82124 does not pro-
cess this information.
Data
is the encapsulated information within the
Ethernet Packet. The ACD82124 does not pro-
cess any of the data information in this field.
FCS
(Frame Check Sequence) is a 32-bit field of
a CRC (Cyclic Redundancy Check) value based
on the destination address, the source address,
the type/length and the data field. The ACD82124
will verify the FCS field for each frame. The pro-
cedure of computing FCS is described in section
of “FCS Calculation.”
Preamble Bit Processing
The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0
bits and there is no limitation on the maximum length of
preamble. After the receive data valid signal RXDV is
asserted by the external PHY device, the port will wait
for the occurrence of the SFD pattern (10101011) and
then start a frame receiving process.
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Source Address and Destination Address
After a frame is received by the ACD82124, the em-
bedded destination address and source address are
retrieved. The destination address is passed to the
lookup table to find the destination port. The source
address is automatically stored into the address lookup
table. For applications that use an external ARL, the
ACD82124 will disable the internal lookup table and
pass the DA and SA to the external ARL for address
lookup and learning.
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INTRODUCTORY
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